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Newbie
dushyanthkinjarapu
Posts: 4
Registered: ‎06-10-2011
0

How to integrate Block memory generated by Core generator in to my top design

Hello Friends,

 

                I am using ISE 13.1 version. I am able to generate core generators but i am unable to integrate it in to my top design. I request you to please help me in integrating IP cores in to my top design.

 

Thanks,

 

Best Regards,

Dushyanth

Expert Contributor
gszakacs
Posts: 5,260
Registered: ‎08-14-2007

Re: How to integrate Block memory generated by Core generator in to my top design

If you highlight the core you added in the Project Navigator there should be a process called

"View HDL instantiation template" which opens a file with the text required to instantiate the

CoreGen module into your design.

 

-- Gabor

 



-- Gabor
Xilinx Employee
dann
Posts: 48
Registered: ‎03-23-2010
0

Re: How to integrate Block memory generated by Core generator in to my top design

Another thing you can do is just generate the core from within ISE instead of seperately, which will automatically integrate it. You'll still need to use the instantiation template to connect it to the rest of your design though.

Xilinx Employee
vsrunga
Posts: 60
Registered: ‎07-11-2011
0

Re: How to integrate Block memory generated by Core generator in to my top design

Hi,

 

You will find core_name.Vho file in the ipcore_dir folder in the project directory.

It contains a componenet and instantiation templates and also some comments on where to paste  the component and instantaition parts in the design file.

Is this what you are looking for or any other hurdle ..

 

Regards,

Vanitha.