System Logic

[a88618688]

Hello, I design a 16*8 sram. When I simulate by Modelsim, it can write 8 bit data into memory . But for the reading, it only reads the first data from the memory(The memory address is from 0 to 7). Can anyone help me find the problem? Thanks.

BEGIN
--Writing Process 
PROCESS(CLOCK) IS
  BEGIN
    If Reset = '1' then
      COUNT <= "00000"; 
        else IF (CLOCK'EVENT AND CLOCK='1') THEN
                 IF(WE='1')THEN
                     IF Count < 8 THEN
                         DATAIN <= ORIGINAL_DATA;
                         RAMTMP(CONV_INTEGER(count))<=DATAIN;
                         count <= count + 1;
                    End if; 
           END IF;
        END IF;
    END IF;
END PROCESS;

--Reading Process
PROCESS(CLOCK) IS
  BEGIN
   If Reset = '1' then
       COUNT <= "00000";
       else IF(CLOCK'EVENT AND CLOCK='1')THEN
                IF (RE='1') THEN
                    IF Count < 8 THEN
                        DATAOUT<=RAMTMP(CONV_INTEGER(count));
                        count <= count + 1;
                    END if;
               END IF;
      END IF;
 END IF;
END PROCESS;
END ARCHITECTURE ART;

[gszakacs]

It's not clear just from the code you posted, but in any case, if these two processes

are in the same architecture, then you are using the same "count" signal for the

address.  VHDL is not case sensitive, so COUNT, Count, and count are all the same.

It's also not clear how you mean that you only read the first data.  In simulation do you

see the read address changing but always read the same value from the memory

array?

Can you post a screen-shot from Modelsim showing the results?

-- Gabor

[a88618688]

The attachment is my test bench waveform. To make you easy understand, I post the whole code. The Count and COUNT is the same signal in the code.

LIBRARY IEEE;
  USE IEEE.STD_LOGIC_1164.ALL;
  USE IEEE.STD_LOGIC_ARITH.ALL;
  USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY DPRAM IS
  GENERIC(WIDTH:INTEGER :=8;
          DEPTH:INTEGER :=16;
          ADDER:INTEGER :=3);
PORT(
     DATAIN:inOUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
     DATAOUT:OUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
     CLOCK:IN STD_LOGIC;
     WE,RE:IN STD_LOGIC;
     RESET: IN STD_LOGIC;
     Original_data : IN std_logic_vector(7 downto 0)
   );
END ENTITY DPRAM;

ARCHITECTURE ART OF DPRAM IS
  TYPE MEM IS ARRAY(DEPTH-1 DOWNTO 0) OF
  STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
  SIGNAL RAMTMP:MEM;
  SIGNAL COUNT: STD_LOGIC_VECTOR(4 DOWNTO 0):="00000";

BEGIN
--Writing Process 
PROCESS(CLOCK) IS
  BEGIN
    If Reset = '1' then
      COUNT <= "00000"; 
        else IF (CLOCK'EVENT AND CLOCK='1') THEN
           IF(WE='1')THEN
              IF Count < 8 THEN
                DATAIN <= ORIGINAL_DATA;
                RAMTMP(CONV_INTEGER(count))<=DATAIN;
                count <= count + 1;
              End if; 
           END IF;
        END IF;
    END IF;
END PROCESS;

--Reading Process
PROCESS(CLOCK) IS
  BEGIN
    If Reset = '1' then
       COUNT <= "00000";
        else IF(CLOCK'EVENT AND CLOCK='1')THEN
                   IF (RE='1') THEN
                       IF Count < 8 THEN
                           DATAOUT<=RAMTMP(CONV_INTEGER(count));
                           count <= count + 1;
                        END if;
                   END IF;
        END IF;
 END IF;
END PROCESS;
END ARCHITECTURE ART;

[a88618688]

For the waveform, the "datain" obtain the data from "Original_data" when "WE" equal to 1. However, the "dataout" can only read the first data of the "datain" when "RE" equal to 1.

[gszakacs]

A couple of points:

1)  If you intend to synthesize the code you posted, you will get errors because the

signal "COUNT" is driven by two processes.  You can only assign a signal from one

process for synthesis.

2) You don't show the signal "COUNT" in your waveform.  I'm guessing that if you do

you will see it go to "XXXXX" after the first read.  I would suggest using two different

signals for read address and write address to clean this up.

-- Gabor

[a88618688]

Thanks, I get the desired results :)

[a88618688]

Almost done! However, it still exists two problems:

1. To read the data from memory, why dataout can not read immediately after reset equal to 1, it starts read data until RE equal to 1 at second time.

2. The dataout is missing the 8th data.

I tried several ways but still can not work it out~

The revised the code as following:

.........

PROCESS(CLOCK) IS
  BEGIN
    If Reset = '1' then
      COUNT_W <= "00000"; 
        else IF (CLOCK'EVENT AND CLOCK='1') THEN
           IF(WE='1')THEN
                IF COUNT_W < 8 THEN
                   DATAIN <= ORIGINAL_DATA;
                  RAMTMP(CONV_INTEGER(COUNT_W))<=DATAIN;
                  COUNT_W <= COUNT_W + 1;
              End if; 
           END IF;
        END IF;
    END IF;
END PROCESS;

--Reading Process
PROCESS(CLOCK) IS
  BEGIN
   If Reset = '1' then
      COUNT_R <= "00000";
        else IF(CLOCK'EVENT AND CLOCK='1')THEN
         IF (RE='1') THEN
           IF COUNT_R < 8 THEN
               DATAOUT<=RAMTMP(CONV_INTEGER(COUNT_R));
               COUNT_R <= COUNT_R + 1;
          END if;
       END IF;
     END IF;
 END IF;
END PROCESS;
END ARCHITECTURE ART;

[vsrunga]

Hi

SRAM can't output data immeadiately after the reset.

Also you are not supposed to assert read/write signal at reset time.

It places data on the bus after recognizing read enable signal. 

As it is synchronous there will be a minimum latency of one clock after read enable is asserted.

So you are viewing the data at second clock.

To discuss on 8th data I am unable to view the Ram address in the attachment.

Regards,

Vanitha.

[gszakacs]

Your processes describe an asynchronous reset (sort of) but only have the

clock in the sensitivity list.  I would suggest using a synchronous reset.

The ISE templates show the suggested form.  In any case your RAM

is in the same process as the address register, and even though it

is not reset when the address counter is reset, it is only assigned

in the "else" clause, so it won't provide an output on the cycle after

reset is asserted.  The ISE templates also show the proper form for

inferring RAMs.  Normally the RAM output (read data) would be in a separate

process without a reset.

A suggestion to make your waveform more readable:  Change the "Radix" setting

for your vectors from binary to hex or unsigned decimal so you can more easily see

what's happening.  Then maybe we can comment on why you don't see the data

at the last read address.

-- Gabor

[a88618688]

I revised the code using synchronous reset. Now I can understand why dataout can read data when RE equal to 1, even if reset is not asserted(This is my first project, I have to use reset in reading data to reach the professor's requirement). The signal Count_a in attachment is just a parameter, so it is useless.

BEGIN
--Writing Process 
PROCESS(CLOCK) IS
  BEGIN
     IF(CLOCK'EVENT AND CLOCK='1') THEN
     If Reset = '1' then
            COUNT_W <= "00000";
            Else IF(WE='1')THEN
               IF COUNT_W < 8 THEN
                   DATAIN <= ORIGINAL_DATA;
                    RAMTMP(CONV_INTEGER(COUNT_W))<=DATAIN;
                   COUNT_W <= COUNT_W + 1;
               End if; 
            END IF;
          END IF;
     END IF;
END PROCESS;

--Reading Process
PROCESS(CLOCK) IS
  BEGIN
   IF(CLOCK'EVENT AND CLOCK='1')THEN
      If Reset = '1' then
         COUNT_R <= "00000";
         else IF (RE='1') THEN
             IF COUNT_R < 8 THEN
                 DATAOUT<=RAMTMP(CONV_INTEGER(COUNT_R));
                 COUNT_R <= COUNT_R + 1;
          END if;
        END IF;
      END IF;
 END IF;
END PROCESS;