System Logic

[ashikinmyms]

Dear respective members,

Kindly need your help. Our design is based on smart card.

Currently, I want to replace old version of module to new one. I get the output hex file from assembly compiler and then I change the hex file to coe file in order to load it in generated IP single port block memory [core generator software].

. im using the same name as the previous one in order to avoid instantiation declaration. As I add the copy source in my design [previously I delete the old version memory file], resynthesize all module,then download the bit file to fpga. Supposedly, the card reader can read the atr code from memory in fpga, but it failed. Is there is any step that i miss?

Really appreciates all your efforts and times. Thanks in advance.

[ashikinmyms]

in summary..

i tried to replace new bootloader file in previous design..i change the coe file and regenerate the block memory using core generator and instantiate it into the design. resynthesize and generate bit file. and download into fpga but the bootloader file supposely give atr reading but it wasnt.. the reader cannot read..is it because the hex to coe file converter failed?as the bootlaoder file is in hex file [output from assembly compiler], i convert it to coe file before load in block memory recustomize method.

[toussaic]

Hi,

You should check the content of the ce file loaded by the ipcoregen by clicking on the "show" button. If the filename in the field is red there must be a problem with the syntax in the coe file.

Each time I change the coe file in a ROM, I relaunch the ipcoregen, rebrowse for the file and look with "show". Then I generate the core. Only way to be sure.

You can check with ISIM your memories contents too.