System Logic

[plpalo]

Hello,

I am using the FIFO generator v8.3 to produce a simple FIFO (8 bits wide, 16 words deep). Assuming that the FIFO is full with data as follows:

d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13, d14, d15

What happens when I enable the wr_en signal for another clock cycle, ignoring the full flag?

I would like to get something like this:

d16, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13, d14, d15

With the d1 byte being the first one to leave the FIFO. Is this what happens or does the internal write pointer become equal to the unmoved read pointer and the FIFO becomes empty again?

[gszakacs]

Actually neither.  Both Coregen and built-in FIFO's gate the write enable with the FULL flag so

writing a full FIFO does nothing.

-- Gabor

[plpalo]

Hello Gabor. Thanks for the quick answer. That's the simplest solution and one that doesn't work with my design. Well, I just need to write my own queue that does what I want. Thanks again.

---

Paweł Prędki

Technical University of Lodz

[gszakacs · Accepted solution]

For a common-clock FIFO, doing what you want should be easy enough to implement.

The problem with independent read and write clocks is that the read and write pointers

are updated on different clock edges, so it's not easy to dump old data by incrementing

the read pointer when a full FIFO is written.

If you need to change clock domains with this FIFO, you might consider using a short

FIFO to change clock domains followed by your queue in the final clock domain.  The

clock-domain crossing FIFO can be constantly read and then the queue is written on

cycles when the FIFO was not empty.  Alternately if you're not very particular abou the

depth at which you dump old data, you could use an almost full flag to force a read

(after resynchronisation to the read clock).

-- Gabor