System Logic

[anikau31]

Hi, I am a final year student doing a project titled Multi ported memory in FPGA. I have a small query regarding the conventional techniques of multi porting memories. I am aware of replication and multi-pumping to increase the number of read and write ports. However I am still confused about the concept of banking. For instance, if I have a single port BLOCK RAM and replicate it to form 1W/2R memory and bank this with another replicated block RAM, will I have 4 memory locations shared between the two writ ports? Please do solve this doubt of mine. If there is any information on the internet, please do let me know as I have found none. Thanks

[eteam00]

The term "bank" is a flexible and imprecise term.  Please describe what "bank" means with more detail.

Or you can describe what you wish to accomplish.  Do you seek a 1W/2R memory?  If so, the simplest design is two BRAMs -- duplicate copies of a single memory -- with the WRITE port connected together (shared WRITE address and WRITE data) while the two READ ports remain independently addressed and accessed.

-- Bob Elkind

[anikau31]

Thank you Mr. Bob for your explaination. 

But what you explained is the process of replication. 1W/ 2R memory. According to some literature which I gathered from some papers, there are three conventional techniques for multiporting memories in FPGA viz. replication, multi pumping and banking.

I plan to design a 4W/8R multi ported memory module. I wish to incorporate replication and banking. 

With a simple example consider I am designing a 2W/2R memory module. First I take a dual port memory BRAM and then  with replication I design a 1W/2R memory module. I take another dual port BRAM and do the same process of replication. Now, if I have to bank these two modules, how will the memory be divided? WIll the write ports write to any memory address now that it is a banked module?

Thanks

[anikau31]

www.eecg.toronto.edu/~steffan/papers/laforest_fpga10.pdf is a paper I am using as base for my project. I hope this helps

[eteam00]

But what you explained is the process of replication. 1W/ 2R memory.

Yes.  This is the simplest implementation, if multiple read ports are needed.

According to some literature which I gathered from some papers, there are three conventional techniques for multiporting memories in FPGA viz. replication, multi pumping and banking.

The paper you linked explains the meaning of "banking".  I am familiar with this approach being called "address segmentation", rather than "banking".

I plan to design a 4W/8R multi ported memory module. I wish to incorporate replication and banking.

With a simple example consider I am designing a 2W/2R memory module. First I take a dual port memory BRAM and then  with replication I design a 1W/2R memory module. I take another dual port BRAM and do the same process of replication. Now, if I have to bank these two modules, how will the memory be divided?

The limitations of such banking schemes must be considered.  If the limitations compromise the rest of your design, then perhaps the rest of your design and/or your multi-porting scheme should be modified.  This is a tradeoff you must make based on your requirements, of which we (forum readers) are almost entirely ignorant.  This is where you, as the designer, may apply any available and possible cleverness which may be at your disposal.

WIll the write ports write to any memory address now that it is a banked module?

In its pure form, "banking" requires that a write to any single address can be completed in only one of the multiple memory banks.  In other words, there is no freedom to direct a write transaction to any of the banked modules.

The paper you linked omits at least two additional memory port multiplication schemes:

• Write port replication, with scoreboarding to track which copy holds the valid (latest) data
• Posted writes, where actual write bandwidth need be no greater than sustained longterm average write activity.

-- Bob Elkind

[anikau31]

Thank you Mr. Bob for your advise.

I tried simulating a 2w/4r banked structure made from true dual port BRAMs. 

The RTL synthesis shows no anomalies and the instantiation seems correct. However no output on my output ports. 

Can you shed some light on any mistake I might have made on the code.

The code for the banked structure is as below:

module banked_memory_2w4r(clock, write_en,addr_0,addr_1,addr_2,addr_3,write_data_0,write_data_1,read_data_0,

read_data_1,read_data_2,read_data_3
);

input clock;

input write_en;

input [7:0]  addr_0;

input [7:0]  addr_1;

input [7:0]  addr_2;

input [7:0]  addr_3;

input [31:0] write_data_0;

input [31:0] write_data_1;

output [31:0] read_data_0;

output [31:0] read_data_1;

output [31:0] read_data_2;

output [31:0] read_data_3;

reg [7:0] muxed_addr_0;
reg [7:0] muxed_addr_1;

try1 bank_0 (
.clock(clock), 
.we_0(write_en),
.we_1(write_en),
.addr_0(addr_0),
.addr_1(addr_1),
.data_0(write_data_0),
.data_1(write_data_1),
.read_data0(read_data_0),
.read_data1(read_data_1)
);

try1 bank_1 (
.clock(clock), 
.we_0(write_en),
.we_1(write_en),
.addr_0(muxed_addr_0),
.addr_1(muxed_addr_1),
.data_0(write_data_0),
.data_1(write_data_1),
.read_data0(read_data_2),
.read_data1(read_data_3)
);

always @(write_en) begin
case(write_en)

1'b1: begin
muxed_addr_0 <= addr_0;
muxed_addr_1 <= addr_1;
end

1'b0: begin
muxed_addr_0 <= addr_2;
muxed_addr_1 <= addr_3; 
end

default: begin
muxed_addr_0 <= addr_2;
muxed_addr_1 <= addr_3;
end

endcase
end

endmodule

Below is the code of true dual port memory in Write First mode

module try1(clock, we_0,we_1, data_0,data_1, addr_0,addr_1, read_data0, read_data1
);

input clock;
input we_0;
input we_1;
input [7:0] addr_0;
input [7:0] addr_1;
input [31:0] data_0;
input [31:0] data_1;

output reg [31:0] read_data0;
output reg [31:0] read_data1;

reg [31:0] ram [0:1023];

always @(posedge clock)
begin
if (we_0) begin
ram[addr_0] <= data_0; 
read_data0 <= data_0;
end
else
read_data0 <= ram[addr_0];
end

always @(posedge clock)
begin
if (we_1) begin
ram[addr_1] <= data_1;
read_data1 <= data_1;
end
else
read_data1 <= ram[addr_1];
end

endmodule

Attached is the screenshot of the testbench results.

[eteam00]

It appears from your simulation that the write enable is never asserted  when needed (on positive edge of the clock).

-- Bob Elkind

[anikau31]

I changed the sensitivity list to include posedge clock. But still I am not able to see any output on my read_ports. 

If you would like to view the testbench, it is given below.

module testering;

// Inputs
reg clock;
reg write_en;
reg [7:0] addr_0;
reg [7:0] addr_1;
reg [7:0] addr_2;
reg [7:0] addr_3;
reg [31:0] write_data_0;
reg [31:0] write_data_1;

// Outputs
wire [31:0] read_data_0;
wire [31:0] read_data_1;
wire [31:0] read_data_2;
wire [31:0] read_data_3;

// Instantiate the Unit Under Test (UUT)
banked_memory_2w4r uut (
.clock(clock),
.write_en(write_en),
.addr_0(addr_0),
.addr_1(addr_1),
.addr_2(addr_2),
.addr_3(addr_3),
.write_data_0(write_data_0),
.write_data_1(write_data_1),
.read_data_0(read_data_0),
.read_data_1(read_data_1),
.read_data_2(read_data_2),
.read_data_3(read_data_3)
);

initial
clock = 1'b0;

always

#50 clock = ~clock;

initial
#100000 $finish;

initial begin

#60 write_en = 1'b1;
#20 addr_0 = 8'b10101010; write_data_0 = 32'd56;
        addr_1 = 8'b11001100; write_data_1 = 32'd44;

#40 write_en = 1'b0;
#20 addr_0 = 8'b11001100;

#40 write_en = 1'b1;
#20 addr_2 = 8'b10101010; write_data_0 = 32'd77;

#20 write_en = 1'b0;
#20 addr_0 = 8'b11001100; addr_2 = 8'b10101010; 
end

endmodule

[eteam00]

I changed the sensitivity list to include posedge clock. But still I am not able to see any output on my read_ports.

Yes, you are seeing output on your read ports.  The output is "U" (undefined).

Your design won't write data to a register unless the write enable is asserted at the positive edge of the RAM/register array clock.  You should know this already, since you wrote the code you posted.  So update your testbench code to provide wider write enable pulses.  If you are going to use the clock construct to generate the write enable input signal, the write enable pulse width should be twice as wide as the clock pulse.

Please, as a favour to everyone reading your posts, format your code in the fixed-pitch COURIER font or use the code button (second icon left of the smiley face in the toolbar).  This will make your posts much more readable, with less effort.

-- Bob Elkind

[anikau31]

I realized my mistake in the testbench. Thanks for pointing it out. 

The design works perfect.  However I have expanded this design to make a 4w/8r memory using true dual BRAMs.

When I synthesize my design I get the following error:

ERROR:Xst:3232 - You are apparently trying to describe a RAM with several write ports for signal <Mram_ram>. This RAM cannot be implemented using distributed resources.

In the process properties window, the RAM inference is set to Block mode. Then why the above error?? I have explicitly defined its inference.

I could post the code, but its too big and has too many modules. If you still need the code I could send it immediately.