Sorry to do this to you, but I don't have the time to reverse engineer your design.
- it would help if you had a block diagram
- it would help if you had comments
- it would help if you pruned all the logic which doesn't bear on the problem you would like verified
- it would help if you included more of the intermediate signals in your simulation trace (e.g. read_3)
I just don't have an hour or two to stare at your code, doing the logic simulation which the logic simulator should be doing for you. My suggestion is to use the logic simulator. If you want to know why a signal changes value, trace the signals which are used to generate the signal in question.
Do you have a routine to initialise the tag memory, or are you depending on the power-up default to initialise the tag memory? The four write ports to the tag memory pretty much requires that the "rat's nest" of logic needs to be simulated. There are no comments which indicate that overlapping (conflicting) writes to the tag memory cannot happen.
-- Bob Elkind
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README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369
Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
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