I am using the xilinx IIC core on a Spartan 3E Starter board. I can write fine
This means that all IIC slave devices signal ACK both
- after receiving the WRITE command
- after receiving WRITE_DATA
Yes?
I could not read a register from an IIC device that requires a read without ACK.
Just to be clear... Which are you saying:
- The slave device will not continue a READ operation once the master signals an ACK?
- The slave device will not signal an ACK (which means it is signaling NACK) after receiving the READ command from the master?
- Something else?
A look at the device datasheet might be helpful. Is the device in question one of the standard IIC devices on the Spartan-3e Starter board?
-- Bob Elkind
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