System Logic

[iimpulse]

I made AXI4 Asyncronous Bridge using FIFO Generator default setting with independant clock.

but i can;t use this IP.  Generated IP's s_axi_rrvalid signal seem  m_aclk syncronous...

therefore s_axi_rrvalid signal in s_aclk domain is not syncronization, AXI4 Bus  encount not correct data.

[iimpulse]

I found m_axi_bready is s_clk sycrononous ,s_axi_bvalid is m_clk syncronous , m_axi_rready is s_clk syncronous and s_axi_rvalid is m_clk syncronous.

i think  s_  prefix domain has to  s_clk sycronous and m_ prefix domain has to m_clk syncronous.

what's wrong???