System Logic

[kahosl]

i'm using spartan-6 the ML605 kit, i will read the document tomorrow, its 2.30 night time here, thanks for the fast reply

[joelby]

ML605 has a Virtex-6 - the document you'll need is UG360.

[ditlegend]

Hm so in other words, my block RAM wont be infered correctly because I
made the process sensitive to the readaddress as below?


architecture Behavior of ram_data is

type ram_type is array (0 to SIZE-1) of std_logic_vector (31 downto 0);
signal ram : ram_type :=
( X"00000063",
X"0000007c",
....
);

begin
PROC_ram : process (clk, rw_addr_cp0)
begin
if (rst = '0') then -- optional reset
data_out_cp0 <= (others => '0');
elsif (clk'event and clk = '1') then
-- memory write:
if (ew_cp0 = '1') then
if (unsigned(rw_addr_cp0) >= 0 and unsigned(rw_addr_cp0) <=
SIZE-1) then
ram(conv_integer(unsigned(rw_addr_cp0))) <= data_in_cp0;
end if;
end if;
end if;

-- memory read:
if (unsigned(rw_addr_cp0) >= 0 and unsigned(rw_addr_cp0) <=
SIZE-1) then
data_out_cp0 <= ram(conv_integer(unsigned(rw_addr_cp0)));
end if;
end process PROC_ram;

end Behavior;

Notice that it is important to register the read address. This is
required to infer block ram. If you don't do that, you will get LUT ram.

[gszakacs]

It looks like you are trying to combine some combinatorial and sequential logic

in the same process.  This is not generally a good idea because the synthesizer

wants to see specific templates to recognize each kind of structure (flip-flop,

RAM, LUTs...).  I would suggest splitting the process into the write process,

which is synchronous to the clock and has only clk (or clk and rst if you really

meant to hava an asynchronous reset) in the sensitivity list, and another

with the read process which is combinatorial and has only the registered

read address in the sensitivity list.  If in doubt, look at the language templates

available from the light-bulb icon in ISE.  They show how to structure your

code so that the appropriate RAM is inferred.

By the way I didn't see from your post how the read address gets registered

to the clock.  This needs to be in the same architecture as the rest of the

memory processes in order for XST to properly infer block RAM.  XST will not

look at the flattened hierarchy when inferring structures like RAM.

-- Gabor