System Logic

[jlqsczw_2007]

Hi,everyone.

I used an ip core of Xilinx---Block memory generator 6.3 to generate a simple dual port RAM.

port A, write first,use ena

port B , read first,always enabled

The wea,ena,clka are all given by DSP device.

The clkb is local clock in FPGA.

After write operation is finished ,DSP give a wr_finish signal.

And I use it to increment the addrb to read data from the port B of dual port RAM.

I use chipscope to watch the signals.

Other data are all right,but the "doutb" of simple dual port RAM is always zero.

Why ???

I noticed that the function model of RAM shows that----

wire [0:0] wea;

So I write it in my code.

And I connected the input WE signal to the wea port of RAM directly.

Will it cause the error ???

[eilert]

Hi,

have you done a simulation to verify the correct behavior of your system?

From the sparse informations you gave nothing much could go wrong, if done correctly.

But a simple offset between write enable and valid data can cause wrong informations (e.g. zeroes) to be stored instead of the right data.

If this works in simulation, then you have reason to trace errors with chipscope.

But if there's some basic mistake in your design, chipscope is a very inconvenient way to find this kind of bug.

Besides, what do you mean with "directly"? From a pad without synchronization and a high delay? This can cause trouble.

Have a nice synthesis

  Eilert