12-17-2009 11:38 AM
I am designing a fairly complex digital down converter chain which employs 200 MHz ADCs, two multi-channel DDS cores (operating at 400MHz clocks) and several multi-channel FIR filter cores (the max number of channels is 6) which operate at 400 or 300 MHZ clocks. The final output data rate for each channel is 10 MHz. The entire design consumes half of DSP48Es and 65-68% of logic on V5SXT95 device. ISE version is 11.4/WinXP32-bit.
I have verified the design in functional simulation. I have now begun testing it on hardware (using LA/Chipscope etc). The results have been ok so far, though I am yet to finish testing the entire design.
However, many a time, even a small change in the design causes the timing score to change drastically. This worries me.
Some of my fellow designers are of the opinion that operating the cores at frequencies like 300/400MHz borders to being insane and day-dreaming. The Xilinx specs do suggest that the FPGA can operate till like 550MHz or so. I read over web that 550MHz is only an indicative figure and anything around that should not be attempted for real designs. However the frequencies that I have in my design are far below than the max freq spec.
So am I over-estimating the potential of V5SXT95 FPGA regarding operation at the above-mentioned frequencies or I can still go ahead without changing my design and trying to fix timing violations?
Kumar Vijay Mishra.
12-17-2009 01:17 PM
A large design with many nets at 300 or 400 MHz may be challenging, but properly done, with pipeline stages placed where needed, is very do-able in Virtex 5. Using more than 80% of all the resources is probably not practical, as more than 80% full will cause there to be problems finding fast paths at these frequencies.
Xilinx San Jose
12-17-2009 02:37 PM
Don't forget to look into your projected power dissipation. A fairly full device of this size switching
at 400 MHz is likely to need active cooling.
12-18-2009 05:59 PM
Possible but likely not fun.
I've seen a ~350MHz design on Virtex-II Pro - but it was pretty much one level of logic between FFs (e.g. very heavily pipelined) and basically a data flow left to right across the chip. I'm sure some level of floor planning was involved too. It actually had considerably more margin based on process, voltage and temperature too before the wheels fell off during testing but offically it supported only that frequency.
More recently I've seen V5 designs running significant portions at 325MHz. One design has many levels of logic and is not necessarily fun to meet timing with respect to floorplanning, implementation options, timing closure, etc. Especially as the part fills up, as Austin said.
A good analogy is like a Mt Everest expedition. It is certainly possible and done relatively frequently to what you might expect but beyond what many are willing to dedicate themselves to. And still a very very small subset of the general population. Ok, maybe not such a good analogy because I'm not aware of any deaths or lost fingers on the FPGA expeditions... Though there have been fingerprints left on the cases by the power dissipation. Make sure you review the XPE spreadsheet at http://www.xilinx.com/power
12-22-2009 01:31 PM
Thank you everyone for your replies.
@Austin: The device utilization is certainly less than 80% in my design (~75%).
@gszakacs: Thanks for the tip. We do have a sound cooling system...I have operated the FPGA for several hours with this design and the temperatures have been under control so far.
@timp: That's what I have been suspecting about. When I read that so-and-so FPGA can operate at 550MHz etc, I ask myself if this speed was obtained by operating...well...an inverter at that speed.While reading the datasheets of, say, a DDS core or FIR compiler, the tables given in the end show the device uitilization for various hardware options. I have seen speeds of 450Mhz being mentioned there. Are those figures obtained from synthesized-and-tested designs?
Also, I discovered that through SmartXplorer (which I had not used when I posted this mail), I could obtain very low timing scores (often, zero or <10) for my designs. If the tool doesn't lie, I should believe that my design would work well (right?). However when I analyze the output of the cores (eg. DDS) through Chipscope Pro, I do not always see exact values as in the functional simulation.
Kumar Vijay mishra.
12-22-2009 01:36 PM
through SmartXplorer (which I had not used when I posted this mail), I could obtain
Correction: through SmartXplorer (which I had not used when I posted my first mail here), I could obtain...
Kumar Vijay Mishra.
12-22-2009 01:45 PM
In fairness to the characterization team here at Xilinx, all the numbers in the data sheet come from measurements of real parts, over the process corners, at the temperature and voltqage extremes, or from circuit simulations using verified device and foundry models (for those things that can not be externally observed).
The numbers in the data sheet form gaurantees, and as such, they are put there with great care.
The global clock tree will run at 550 MHz, for more than 20 years, at 85C, and highest operating core voltage ...
Now, what you can do with that, is of course limited by the delays in connecting things together! But, we have designs that show some pretty useful things running at these speeds (DSP, math, etc.).
On every lot, we monitor the transistor and process for excursions, and we test every part to specification. Not every specification, but enough to be sure we meet our shipped quality levels, and that the customers will be happy.
I have blogged in the past on the shipped quality levels, and since we have acheived levels below a few parts per million defect level, our quality level is second to none.
Xilinx San Jose
12-22-2009 01:58 PM
Thank you Austin for frankly putting things in perspective. I gather then (a) that if the timing score is indeed zero, I must believe the tool. (b) it is not unrealistic or super-duper-tough to design with 300-400Mhz clock speeds. Would you please give the links to those high-frequency designs that you mentioned in your post or point me to some other rxilinx esource which could be helpful while designing at such clock speeds.
Kumar Vijay Mishra.
12-22-2009 02:10 PM
I suggest you contact your distibutor or Xilinx Field Applications Engineer. This is not the sort of thing we just hand out at random without some consultation and guidance.
I think others have posted that it is do-able, but no "walk in the park."
By the way, the timing report will tell if things are OK or not: the slack you have should be at least 1/2 the peak to peak system jitter in order to be in the safe region. For example, if system jitter and noise is 500 ps, peak to peak, then the slack must be greater than 250 ps on all paths. At 500 MHz, the most common problem after just not meeting timing (or not realizing you have a critical path that was uncontrained), is a failure to take into account the system noise and jitter which is unavoidable as IOs and core elements (and other circuits on your board) switch.
Xilinx San Jose