Timing Analysis

[ppaysarvi]

I found a bug in the ISE timing analyzer. Sometimes, when it is calculating the slack it doesn't take into account the "Clock Arrival" parameter. For example, when I want to design the ADC interface in the FPGA, I usually use a DCM to advance or delay the ADC clock in order to meet timing. However, sometimes the timing analyzer doesn't see the DCM phase adjustment and reports that those paths are failing.

Another instance is when I want to design a DDR output interface. In order to do that, again, I use a DCM to generate two clocks, one with 0 degree phase and the other one with 90 degree phase. I use the 0 degree clock to clock the data lines and use the 90 degree clock to generate DDR clock. In this case, again, the timing analyzer doesn't report the "Clock Arrival" for the DDR clock. I am using ISE 13.2

[eteam00]

Have you opened a webcase so that the Xilinx folks can confirm the bug (and its presence in 13.4 and 14.1 software), and enter the bug fix in the software developement queue?

For the forums folks, a simple example would be helpful, if you have one.

-- Bob Elkind

[chrisz_dup]

Also make sure that the OFFSET IN/OUT is not using the HIGH/LOW keywords.  The HIGH/LOW keywords on the OFFSET IN/OUT will remove the phase shifting of the DCM/PLL/MMCM.