Timing Analysis

[sharad_snh]

Hi,

  I am interested in finding out the delay variations in Xilinx primitives as PVT varies. Where can I get this information? I would like to know the best case and the worst case delay of elements.

Regards,

Sharad

[eteam00]

I would like to know the best case and the worst case delay of elements.

These are located in the device family datasheets.  Additional information can be gleaned from the device IBIS models.

If a minimum delay is not specified, you must assume that it is zero.  This is typical of CMOS components datasheets.

Generally speaking, a 'missing' specification is either not characterised, not tested in production, or not guaranteed.

The general rule of thumb for CMOS devices is that:

• Increasing voltage will reduce delays.
• Reducing die temperature will reduce delays. (this is the opposite of the effect of temperature on bipolar devices)

Note:  I am not a Xilinx employee, and I do not represent Xilinx.

-- Bob Elkind

[sharad_snh]

Hi Bob,

  Thanks for that piece of info. As far as  I know, the datasheet does not give the delay characteristics in detail of all the elements. I just went through the V4 datasheet and then ran speedprint as well to get the delay characteristics for XC4VLX25 for speed grade -12 and I can see that the speedprint utility gave far more information. It is also mentioned on xilinx website that the values reported by the speedprint utility will override the values in the datasheet. While datasheet has more information to understand what the reported values mean, the speedprint simply gives values and it is difficult to make sense of phrases like Tickce, Tidlo, Tidlod etc. in the speedprint file.

 I also had a look at the simprim library. I will show below the specify block for two modules:

X_LUT5:

specify

 (ADR0 => O) = (0:0:0, 0:0:0);  

(ADR1 => O) = (0:0:0, 0:0:0);

 (ADR2 => O) = (0:0:0, 0:0:0);

  (ADR3 => O) = (0:0:0, 0:0:0);

 (ADR4 => O) = (0:0:0, 0:0:0);  

specparam PATHPULSE$ = 0;

  endspecify

X_FDD:

specify

 (CLK => O) = (100:100:100, 100:100:100);  

(SET => O) = (0:0:0, 0:0:0);

 (RST => O) = (0:0:0, 0:0:0);

--------

I am not able to figure out the path from values reported in the simprim library and to those in speedprint file. The reason I am looking into all of these is because I want to do an early estimation of timing of my design without running synthesis and PPR. Since, Xilinx already provides all the delay values (but figuring out the relationship has so far been tough for me), it might be possible to do some early estimate. I understand very well that this early estimate will lack routing delays.

I also had a look at IBIS model file (of V4). It has information related only to the I/O standards and does not serve my purpose a lot.

[eteam00]

While datasheet has more information to understand what the reported values mean, the speedprint simply gives values and it is difficult to make sense of phrases like Tickce, Tidlo, Tidlod etc. in the speedprint file.

Does the datasheet help make sense of phrases like Tickce, Tidlo, Tidlod etc. which appear in the speedprint file?

-- Bob Elkind

[sharad_snh]

Yes, some parameters like Tidlo ,Tidlod etc. exist both in datasheet and speedprint output but others like Tifbq, Tifbo exist only in speedprint output. Basically, we have 3 sources of info:

1)Datasheet values

2)Speedprint file output

3) specify block in simprim.

I am looking for the connection between these or at least which one to use to do early estimation.

[eteam00]

Suggestion:

Open a webcase for direct support from Xilinx.

Include in the webcase:  where is the glossary or definition table for the speedprint output parameters?

If the missing definitions aren't really missing, then please post to this thread what you learned.

If the missing definitions are an oversight in speedprint, then the webcase should provoke a document or software tools change request, which should (in the long run) fix the problem.  This is the sort of problem which should be fixed in the tool, and a user forum post is not a proper solution.

Thank you for bringing this up.  I was not aware of speedprint before reading your thread.

-- Bob Elkind

[sharad_snh]

Bob, I have opened a webcase. I will update this thread once I get a response from Xilinx. Thanks for your help so far!

[bassman59]

---

sharad_snh wrote:

Yes, some parameters like Tidlo ,Tidlod etc. exist both in datasheet and speedprint output but others like Tifbq, Tifbo exist only in speedprint output. Basically, we have 3 sources of info:

1)Datasheet values

2)Speedprint file output

3) specify block in simprim.

I am looking for the connection between these or at least which one to use to do early estimation.

---

One can generally assume that the values used by the software tools for the timing analysis are the most up-to-date, assuming you regularly update your software with service packs.

FWIW, trying to estimate timing of your design from data sheet values without actually doing the place and route can be a fool's errand. Not specified in the data sheets are the particular routing delays your design might incur. For example, I just spent a day trying to close timing on a 200 MHz design that I thought would be no sweat for the S6, and it turned out that a particular coding style lead to an excessive delay path for a few signals. Yes, it was really weird, but beware of routing delays when wagging a timing estimate.

[gszakacs]

Just some further observations:

Advanced deep submicron CMOS does not exhibit the same temperature curves

as earlier CMOS.  In particular cooling the device does very little to speed it up

once you get below room temperature.

The IBIS models are for I/O, and it was probably reasonable for Bob to assume you

were talking about I/O when discussing the delay of primitives.  Most people

let the normal tool flow handle the internal timing.  If you're planning to use LUT

primitives for delays, then you will have a lot of headaches in store for you.  Modern

devices have much larger delays in routing that in the slice elements.  Getting any

sort of repeatable results using internal elements for delay requires a lot of hand

tweaking of the design layout and routing.

-- Gabor

[eteam00]

Advanced deep submicron CMOS does not exhibit the same temperature curves as earlier CMOS.  In particular cooling the device does very little to speed it up once you get below room temperature.

Well, how often is the die temperature of an FPGA lower than room temperature?

In general, CMOS circuits which carry considerable current or operate at higher voltages (e.g. IO buffers, and internal line drivers and clock drivers) are still affected by die temperature.

The circuits which use minimum geometry (deep submicron) devices and operate at low voltages (e.g. LUTs powered by VCCINT) -- as Gabor correctly advises -- exhibit performance which is mostly insensitive to die temperature variations.

These are somewhat vague generalities.  There is an abundance of academic papers on this subject.

The days of heat guns and freeze spray are not quite over...  yet.

-- Bob Elkind