Timing Analysis

[bsvi]

Hi!

I have 12Mhz clock and DCM that produces 144Mhz clock. At system's startup 12Mhz domain shifts out configuration word that is used by 144Mhz domain until shutdown.

Obviously, I have to add configuration registers in 144Mhz time ignore group:

NET "_cpu/config_register/*" TIG = TS_hf_clk01; (TS_hf_clk01 is 144Mhz clock timespec)

I get lots of warning similar to this:

ConstraintSystem:67 - Constraint <PIN "_cpu/config_register/out_174_pins<3>" TIG = TS_hf_clk01;> [UTC.pcf(887)] modifies the effective value of constraint <TS_hf_clk01 = PERIOD TIMEGRP "hf_clk01" TS_Period_1 / 15 HIGH 50%;> [UTC.pcf(391)].

But that's what I supposed to do! How can I disable this warning? I tryed to Filter it out, but had no success (I'm able to filter out all warnings except for this one).

Thenk you!

[bsvi]

I'v managed to solve this issue by specifying (excessive) datapath delay:

NET "clk_12MHz" TNM_NET = FFS "CPU_CLK_GRP";
NET "hf_clk0" TNM_NET = FFS "HF_CLK_GRP";
TIMESPEC TS_cpu_to_hf = FROM "CPU_CLK_GRP" TO "HF_CLK_GRP" 1000 ns DATAPATHONLY;