Timing Analysis

[sulilittle]

Hi,

I use ISE13.3 and my board is virtex-6 xc6vlx240t-ff1156-2.I use DSP48E1 to implement 51-step FIR.Now ,the rst of the top design to the FIR display HOLD violations,as follows, beacause the source clock and the destination clock come from different DCM.I constraint them like this:

NET "CLK60M" TNM_NET="CLK60MGrp";

NET "CLK540M" TNM_NET="CLK540MGrp";

TIMESPEC TS_Asynchpath=FROM CLK540MGrp TO CLK60MGrp 14.815 ns DATAPATHONLY;

IS this right? Thank you very much!

--------------------------------------------------------------------------------
 
 Hold Paths: Unconstrained path analysis
 
 --------------------------------------------------------------------------------
 
 Paths for end point u_half_phase/u_half_phase_ip/u_fir_unit_gen[42].u_fir_unit/DSP48E1_inst (DSP48_X3Y45.RSTALLCARRYIN), 1 path
 --------------------------------------------------------------------------------
 Slack (hold path):      -0.517ns (requirement - (clock path skew + uncertainty - data path))
   Source:               rst (FF)
   Destination:          u_half_phase/u_half_phase_ip/u_fir_unit_gen[42].u_fir_unit/DSP48E1_inst (DSP)
   Requirement:          0.000ns
   Data Path Delay:      0.919ns (Levels of Logic = 0)
   Clock Path Skew:      0.746ns (3.785 - 3.039)
   Source Clock:         clk60M rising
   Destination Clock:    clk540M rising
   Clock Uncertainty:    0.690ns
 
   Clock Uncertainty:          0.690ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
     Total System Jitter (TSJ):  0.070ns
     Discrete Jitter (DJ):       0.274ns
     Phase Error (PE):           0.548ns
 
   Minimum Data Path at Slow Process Corner: rst to u_half_phase/u_half_phase_ip/u_fir_unit_gen[42].u_fir_unit/DSP48E1_inst
     Location                  Delay type         Delay(ns)  Physical Resource
                                                             Logical Resource(s)
     ------------------------------------------------------  -------------------
     SLICE_X68Y115.AQ          Tcko                  0.259   rst
                                                             rst
     DSP48_X3Y45.RSTALLCARRYIN net (fanout=7694)     0.872   rst
     DSP48_X3Y45.CLK           Tdspckd_RSTALLCARRYIN_MREG(-Th)     0.212   u_half_phase/u_half_phase_ip/u_fir_unit_gen[42].u_fir_unit/DSP48E1_inst
                                                             u_half_phase/u_half_phase_ip/u_fir_unit_gen[42].u_fir_unit/DSP48E1_inst
     ------------------------------------------------------  ---------------------------
     Total                                           0.919ns (0.047ns logic, 0.872ns route)
                                                             (5.1% logic, 94.9% route)
 
 --------------------------------------------------------------------------------
 
 Paths for end point u_half_phase/u_half_phase_ip/u_fir_unit_gen[43].u_fir_unit/DSP48E1_inst (DSP48_X3Y46.RSTALLCARRYIN), 1 path
 --------------------------------------------------------------------------------
 Slack (hold path):      -0.511ns (requirement - (clock path skew + uncertainty - data path))
   Source:               rst (FF)
   Destination:          u_half_phase/u_half_phase_ip/u_fir_unit_gen[43].u_fir_unit/DSP48E1_inst (DSP)
   Requirement:          0.000ns
   Data Path Delay:      0.927ns (Levels of Logic = 0)
   Clock Path Skew:      0.748ns (3.787 - 3.039)
   Source Clock:         clk60M rising
   Destination Clock:    clk540M rising
   Clock Uncertainty:    0.690ns
 
   Clock Uncertainty:          0.690ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
     Total System Jitter (TSJ):  0.070ns
     Discrete Jitter (DJ):       0.274ns
     Phase Error (PE):           0.548ns
 
   Minimum Data Path at Slow Process Corner: rst to u_half_phase/u_half_phase_ip/u_fir_unit_gen[43].u_fir_unit/DSP48E1_inst
     Location                  Delay type         Delay(ns)  Physical Resource
                                                             Logical Resource(s)
     ------------------------------------------------------  -------------------
     SLICE_X68Y115.AQ          Tcko                  0.259   rst
                                                             rst
     DSP48_X3Y46.RSTALLCARRYIN net (fanout=7694)     0.880   rst
     DSP48_X3Y46.CLK           Tdspckd_RSTALLCARRYIN_MREG(-Th)     0.212   u_half_phase/u_half_phase_ip/u_fir_unit_gen[43].u_fir_unit/DSP48E1_inst
                                                             u_half_phase/u_half_phase_ip/u_fir_unit_gen[43].u_fir_unit/DSP48E1_inst
     ------------------------------------------------------  ---------------------------
     Total                                           0.927ns (0.047ns logic, 0.880ns route)
                                                             (5.1% logic, 94.9% route)
 
 --------------------------------------------------------------------------------
 
 Paths for end point u_half_phase/u_half_phase_ip/u_fir_unit_gen[42].u_fir_unit/DSP48E1_inst (DSP48_X3Y45.RSTM), 1 path
 --------------------------------------------------------------------------------
 Slack (hold path):      -0.504ns (requirement - (clock path skew + uncertainty - data path))
   Source:               rst (FF)
   Destination:          u_half_phase/u_half_phase_ip/u_fir_unit_gen[42].u_fir_unit/DSP48E1_inst (DSP)
   Requirement:          0.000ns
   Data Path Delay:      0.932ns (Levels of Logic = 0)
   Clock Path Skew:      0.746ns (3.785 - 3.039)
   Source Clock:         clk60M rising
   Destination Clock:    clk540M rising
   Clock Uncertainty:    0.690ns
 
   Clock Uncertainty:          0.690ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
     Total System Jitter (TSJ):  0.070ns
     Discrete Jitter (DJ):       0.274ns
     Phase Error (PE):           0.548ns
 
   Minimum Data Path at Slow Process Corner: rst to u_half_phase/u_half_phase_ip/u_fir_unit_gen[42].u_fir_unit/DSP48E1_inst
     Location             Delay type         Delay(ns)  Physical Resource
                                                        Logical Resource(s)
     -------------------------------------------------  -------------------
     SLICE_X68Y115.AQ     Tcko                  0.259   rst
                                                        rst
     DSP48_X3Y45.RSTM     net (fanout=7694)     0.932   rst
     DSP48_X3Y45.CLK      Tdspckd_RSTM_MREG(-Th)     0.259   u_half_phase/u_half_phase_ip/u_fir_unit_gen[42].u_fir_unit/DSP48E1_inst
                                                        u_half_phase/u_half_phase_ip/u_fir_unit_gen[42].u_fir_unit/DSP48E1_inst
     -------------------------------------------------  ---------------------------
     Total                                      0.932ns (0.000ns logic, 0.932ns route)
                                                        (0.0% logic, 100.0% route)

[gszakacs]

TIMESPEC TS_Asynchpath=FROM CLK540MGrp TO CLK60MGrp 14.815 ns DATAPATHONLY;

This is correct if you want to consider the two clocks as unrelated and asynchronous.  Otherwise

you should not have DATAPATHONLY.  DATAPATHONLY prevents hold time checking during

place & route.

Hold Paths: Unconstrained path analysis
 

Note that the "errors" are in unconstrained paths.  These will not affect the timing score

reported by Place & Route, and should not cause Place & Route to spend extra time to

mitigate them.  These paths are not covered by the above constraint as they are going

from the CLK60M to the CLK540M domain rather than the other way around.  If you don't

want to see these "errors" in the timing report, then you need to add another FROM TO

constraint like:

TIMESPEC TS_Reversepath=FROM CLK60MGrp TO CLK540MGrp 14.815 ns DATAPATHONLY;

-- Gabor

[sulilittle]

Thank you very much!

I want to say,two clocks from different DCMs, should not conside them as unrelated or asynchronous?

In a project,the sub-module have synchronous reset and asynchronous reset,is it right? Does it can affect the timing?As now I have two signals ,they have the same processing style,but one signal is steady,but the other have timing problem,I do not know why. In my opinion, it should the timing  problem,so I add the Unconstrained path to  analysis the timing,may I?