Timing Analysis

[guyeschemann]

I'm assuming a minimal design consisting of PAD -> FF -> FF -> PAD. Here is the VHDL source code:

entity toplevel is
  port (i_clk  : in  std_logic;
        i_data : in  std_logic;
        o_data : out std_logic);
end toplevel;

architecture Behavioral of toplevel is

  signal s_data_r  : std_logic := '0';
  signal s_data_r1 : std_logic := '0';

begin

  process(i_clk)
  begin
    if rising_edge(i_clk) then
      s_data_r  <= i_data;
      s_data_r1 <= s_data_r;
    end if;
  end process;

  o_data <= s_data_r1;

end Behavioral;

I'm constraining the PAD -> FF, FF -> FF and FF -> PAD paths as follows:

NET "i_clk" TNM_NET = i_clk;
TIMESPEC TS_i_clk = PERIOD "i_clk" 100 MHz HIGH 50%;
NET "i_data" OFFSET = IN 5 ns VALID 5 ns BEFORE "i_clk" RISING;
NET "o_data" OFFSET = OUT 7 ns AFTER "i_clk";

When I turn on the "report unconstrained paths" in the Timing Analyzer,  I see unconstrained paths from the clock input pad to the FFs:

 ================================================================================ 
 Timing constraint: Unconstrained path analysis  
  2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints 
  0 timing errors detected. (0 setup errors, 0 hold errors) 
  Maximum delay is   2.606ns. 
 -------------------------------------------------------------------------------- 
  
 Paths for end point s_data_r1 (SLICE_X16Y2.CLK), 1 path 
 -------------------------------------------------------------------------------- 
 Delay (setup path):     2.606ns (data path) 
   Source:               i_clk (PAD) 
   Destination:          s_data_r1 (FF) 
   Data Path Delay:      2.606ns (Levels of Logic = 2) 
  
   Maximum Data Path at Slow Process Corner: i_clk to s_data_r1 
     Location             Delay type         Delay(ns)  Physical Resource 
                                                        Logical Resource(s) 
     -------------------------------------------------  ------------------- 
     K3.I                 Tiopi                 0.790   i_clk 
                                                        i_clk 
                                                        i_clk_BUFGP/IBUFG 
                                                        ProtoComp1.IMUX 
     BUFGMUX_X3Y13.I0     net (fanout=1)        0.749   i_clk_BUFGP/IBUFG 
     BUFGMUX_X3Y13.O      Tgi0o                 0.209   i_clk_BUFGP/BUFG 
                                                        i_clk_BUFGP/BUFG 
     SLICE_X16Y2.CLK      net (fanout=2)        0.858   i_clk_BUFGP 
     -------------------------------------------------  --------------------------- 
     Total                                      2.606ns (0.999ns logic, 1.607ns route) 
                                                        (38.3% logic, 61.7% route) 
  
 -------------------------------------------------------------------------------- 
  
 Paths for end point s_data_r (SLICE_X16Y13.CLK), 1 path 
 -------------------------------------------------------------------------------- 
 Delay (setup path):     2.606ns (data path) 
   Source:               i_clk (PAD) 
   Destination:          s_data_r (FF) 
   Data Path Delay:      2.606ns (Levels of Logic = 2) 
  
   Maximum Data Path at Slow Process Corner: i_clk to s_data_r 
     Location             Delay type         Delay(ns)  Physical Resource 
                                                        Logical Resource(s) 
     -------------------------------------------------  ------------------- 
     K3.I                 Tiopi                 0.790   i_clk 
                                                        i_clk 
                                                        i_clk_BUFGP/IBUFG 
                                                        ProtoComp1.IMUX 
     BUFGMUX_X3Y13.I0     net (fanout=1)        0.749   i_clk_BUFGP/IBUFG 
     BUFGMUX_X3Y13.O      Tgi0o                 0.209   i_clk_BUFGP/BUFG 
                                                        i_clk_BUFGP/BUFG 
     SLICE_X16Y13.CLK     net (fanout=2)        0.858   i_clk_BUFGP 
     -------------------------------------------------  --------------------------- 
     Total                                      2.606ns (0.999ns logic, 1.607ns route) 
                                                        (38.3% logic, 61.7% route) 
  
 -------------------------------------------------------------------------------- 

How do I get rid of these? Is it at all possible to achieve zero unconstrained paths in a design?

Thanks,

Guy.

[guyeschemann]

Just noticed that adding the following constraint gets me to zero unconstrained paths without overriding the PERIOD constraint. Is there maybe a better way to achieve that?

INST "i_clk" TNM = PADS "TNM_I_CLK";
TIMESPEC "TS_I_CLK_TO_FFS" = FROM "TNM_I_CLK" TO "FFS" TIG;

Thanks,

Guy.

[austin]

Guy,

Unconstrained does not mean "bad."

You must analyze all paths. The ones that really do not ned to be constrained may use the timing ignore (as you have done), or you may just ignore them, after you have checked them in the report.

[guyeschemann]

Hi Austin,

I understand that not all unconstrained paths are bad. But some of them may be. I do a lot of design reviews, and in a typical design with tens of thousands of unconstrained paths, I just can't go through every path and check whether it is good or bad. That's why I'm looking for ways to reduce the unconstrained paths count to a manageable number.

Thanks,

Guy.

[chrisz]

Xilinx recommends not using a FROM:TO:TIG constraint on the clock path.  Yes, this will remove it from the Unconstrained Path Report, but it will also remove the clock network from the clock skew analysis.  Xilinx recommends using a FROM:TO constaint with a large requirement, so the clock skew analysis is not impacted. 

[guyeschemann]

Well, that's an interesting information. Is there a document where I can read more about this?

Thanks for your support,

Guy.

[chrisz]

A lot of this information is in TIming Constraints User Guide (UG612): http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_2/ug612.pdf