Timing Analysis

[jlqsczw_2007]

Hello,everyone. How to design such a  Asynchronous interface below ? Please help me.

DSP and FPGA

DSP uses 100M emif_clock to write data to FPGA,

Then FPGA uses 200M internal clock to read the data.,does something ,writes them to several FIFOs and informs DSP to read them.

Finally DSP uses 100M emif_clock to read data from FPGA,

There are three kinds of  Asynchrnous data to FPGA----

control signals ---- CE, OE, SEL[1:0]

address ----- dsp_addr[19:0]

data------ dsp_data[31:0]

For example ,let's see the DSP READ operation.

Although FIFO can reduce the probablity of metastability, but the data read from FIFO,which we may call it "fifo1_dout","fifo2_dout",.....  have to do something  to be transfered to dsp data bus.

1)

always @(posedge emif_clk)

 if(SEL == 2'b01)

begin

 case(dsp_addr[19:16])

4'b0:  dout_temp <= fifo1_dout;

 4'b1:  dout_temp <= fifo2_dout;

 4'b2:  dout_temp <= fifo3_dout;

 ...

endcase

end

2)

 inout dsp_data;

...

wire dsp_en;

assign dsp_en = (!CE) & (!OE);

assign dsp_data = dsp_en ? dout_temp : 32'hz;

Now I have seen the right data on "fifo1_dout","fifo2_dout",....., and the wrong data on "dsp_data" with chipscope. The timing report does not report any error so I guess maybe the metastability lead to the problem.

Since the emif_clk,SEL,dsp_addr,CE,OE,...are all Asynchronous to FPGA, and these HDL codes above do not do anything to deal with it. So how can I write HDL codes to reduce the probablity of metastability and make the interface reliable  ???

[bwiec]

I think this might help:

http://www.sunburst-design.com/papers/CummingsSNUG2008Boston_CDC.pdf

[hgleamon1]

If the interface is asynchronous (you mention clocks in both the FPGA and the DSP but don't list these clocks as signals that are transmitted between the two devices) then the interface should have a timing diagram associated with the control signals that you describe. You haven't mentioned what DSP device you are using so I cannot look at a datasheet.

The snippet of code you have provided doesn't really deal with the relative timing of CS, OE and SEL[1:0], as well as the address and data busses. How these signals operate relative to each other will be critical to your interface success, i.e. WHEN is data expected to be valid?

As suggested, once these signals enter the FPGA, you should probably synchronise them to the FPGA clock. I'm not sure that a FIFO will help (unless you wish to store data entirely within the FPGA clock domain) - which clock(s) will you use to clock the data in and out?

Regards,

Howard

[xingzhe]

you could check on signal dout_temp and dsp_en, which may require correct behaviour of signal dsp_addr and SEL, which need to be synchronous to the emif_clk clock domain.