04-09-2009 11:20 PM
After the implementation of my project, I read the detailed report in the FPGA Design Summary. And in the [Synthesis Report], I can see the following information:
Timing constraint: Default period analysis for Clock 'clk'
Clock period:1.778ns (frequency:562.430 MHz)
And in the [Static Timing Report], I can see the following information:
Timing constraint: TS_clk = PERIOD TIMEGRP "clk" 8 ns HIGH 50%;
3 paths analyzed, 2 endpoints analyzed, 0 failing endpoints
Minimum period is 1.305ns.
So I notice the period in the two report is different. Firstly I guess maybe it is because the UCF will not influence the process of synthesis but will influence the process of implementation. So afterwards I delete all the constraits, and the static timing report has changed. But it is still different from those information in the synthesis.
I guess the "Minimum period" in the [Static Timing Report] is more accurate. So my question is what's the meaning of "Clock period" in the synthesis especially considering it is a little longer than the one of the Static Timing Report. Which information can we get from it and how to explain the difference betweenn the two clock period in [Synthesis Report] and [Static Timing Report]?
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04-10-2009 05:52 AM
The synthesis report is only an estimate, e.g. it doesn't have actual routing delays at this point and there are some optimizations that can also take place in map. It is there so you have an initial estimate for comparison, but it is not generally the figure of merit.
The static timing report is the one you generally are interested in (though it obviously takes place later in the design). The tools are timing driven, so I would expect a change in the static timing report if you deleted constraints, changed the input design, changed the implementation settings, etc.