Timing Analysis

[a9909928]

Hi,

I'm using Virtex 5 110t1136 board, and I wish to lower clock freqency (25 MHz) to 2Mhz in system generaor, how could I do that?

I know some techniques such as using dividers and counters, but I don't know how to implemment it.

How can I find the clock frequency in system generator becasue most of my designs are about mathmetic equations, I don't know how to change clock frequency in system generator.

Thanks a lot.

Ryan

[bwiec]

You can set the clock frequencies in the SysGen Token and you can edit your sampling frequencies at the Gateway In blocks

[ajmirg · Accepted solution]

For low frequencies, you may use clock enable. Make a search for 'clock enable' from:

http://www.xilinx.com/support/documentation/sw_manuals/sysgen_user.pdf

Cheers,

[a9909928]

Thanks a lot.