Timing Analysis

[thothoswep]

Hi,

My application is source synchronous. My design has a input bus and clk driven by an external device.

The input clk is connected to a PLL_ADV. 

I have a input clock contraint defining the period.

How can i constraint the input bus? I cannot use the input clock because there is a restriction when using PLLs that  states that i can only define the period contraint and can't use it  for anything else, right?

I understand that the clock constraint propagates through the PLL outputs...but i need to contraint the inputs in the ucf

What is the best approach?

so far , i added maxdelay to the bus to make sure the input skew is small. Then, using DRP control the phase in order to choose the best phase to capture the input bus

Is this correct? Are there better options?

[eteam00]

Have you looked at the OFFSET IN timing constraint?

It might be helpful if you specify the input data bit rate and the source clock frequency (e.g. SDR vs. DDR).

Also, which device family are you targeting?

-- Bob Elkind

[ajmir]

I would suggest that you read page 11-12 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_2/ug612.pdf

The tool supports the use of OFFSET IN for an input register clocked by PLL-generated clock. The tool will compute the full clock path through the PLL along with the correct period and clock arrival. Note that you always use a clock from an input pad for OFFSET.