Timing Analysis

[shobhit6993]

Hello

I am working on a project which requires the use of onboard ADC on the Spartan 3E starter kit. According to the manual(ug230), the pre-amplifier supports a clock frequency of about 10 MHz(max)(page-79). But for the ADC chip, the min time period of SPI-CLK is given to be 19.6ms(fig 10-7 page 80) but a time period of min 4ns for AD_CONV(same figure) is mentioned. Also, it is mentioned on page-79 that the max sample rate of ADC is approx 1.5Mhz. What should be the optimum clock frequency for both amplifier and ADC to function properly, which may take care of the different frequency requirements of different signals? Any valuable and quick suggestions will prove to be extremely useful as its urgent!!

[eteam00 · Accepted solution]

... the pre-amplifier supports a clock frequency of about 10 MHz(max)(page-79).

The LTC6912 amplifier SPI interface is used to set gain.  When the LTC6912 is not selected, the LTC6912 ignores the SPI clock input.  When the LTC6912 is selected, then the SPI clock frequency must be 5MHz or less.  This is per the LTC6912 datasheet (page 11).  On the Starter Kit, the LTC6912 is powered with single-ended 3.3V (not 5V or dual +/- 5V), and 3.3V operation is slower than 5V operation for this device.

A quote from UG230 v1.2, page 79:

The amplifier interface is relatively slow, supporting only about a 10 MHz clock frequency.

In this case, UG230 is in error.  The maximum LTC6912 SPI clock frequency is 5MHz, not 10MHz.  From the LTC6912 datasheet:

But for the ADC chip, the min time period of SPI-CLK is given to be 19.6ms(fig 10-7 page 80)

This figure is 19.6 nS, not 19.6 mS.

but a time period of min 4ns for AD_CONV(same figure) is mentioned.

This is the minimum pulse width of the AD_CONV input signal, not the AD_CONV period.

Also, it is mentioned on page-79 that the max sample rate of ADC is approx 1.5Mhz. What should be the optimum clock frequency for both amplifier and ADC to function properly, which may take care of the different frequency requirements of different signals?

When accessing the amplifier, use a SPI clock frequency suitable for the amplifier.  When accessing the ADC, use a  SCK frequency suitable for the ADC.

Normally the ADC is not being used when the amplifier is being reconfigured through the SPI interface.  Normally when the ADC is being used, the amplifier SPI interface is not being used, and the amplifier SPI port is de-selected (and the amplifier will ignore the SPI clock, at any frequency).

You should have the flexibility in your state machine design to control the serial clock frequency independently for each of the devices being accessed.

Read the ADC datasheet for helpful information on how to control the ADC and its CONV and SCK inputs.  The timing characteristics table on page 5 confirms 1.5MHz maximum sampling frequency, 50MHz SCK clock frequency, and minimum conversion time of 32 SCK clock cycles.

From the New User Forum README thread (post #2, the mini-FAQ) is this entry, with some (possibly) helpful links:

care and feeding of ADC, pre-amp, and DAC on many Xilinx development boards link#1  link#2  link#3  link#4

-- Bob Elkind

[shobhit6993]

Thank you very much for such a quick, descriptive and helpful reply!!

[ashish23345]

Hello Sir

  I am currently working on FPGA receiver project. In which i will receive signal in between 136-174 MHz frequency.  These signal doesn't contain any information, only a pulse signal.  To check out the presence of signal in that range.

so my question is can spartan 3E kit directly process these high frequency signal or i have to firstly down converted?

there is any  option through which i avoid down conversion, because it doesn't contain any signal.  Only a unmodulated sine/pulse signal.