Timing Analysis

[jgomezco]

Hi,

I have a design (Spartan 3-AN) where I have several cross-clocks domains. Normally I manage to set-up TIG using the Create-Timings-Constraints options of ISE 13.2 but with the following system it is not possible:

- I have two clocks (detected automatically by ISE), named:

RegFGC3_DCM_eng_CLK2X_BUF = generated from a DCM

testpoint_isf_ctrl(14) = generated by a State Machine, used internally in a VHDL module and then sent to the output of the VHDL module via a vector. I think that’s why ISE retains that last name ….

Using the standard options of Create-Timings-Constraints, I have the following lines on the ucf file

Created by Constraints Editor (xc3s700an-fgg484-4) - 2011/10/20

NET "FPGA_SCIVS_MODE" TNM_NET = FPGA_SCIVS_MODE;

TIMESPEC TS_FPGA_SCIVS_MODE = PERIOD "FPGA_SCIVS_MODE" 10 MHz HIGH 50%;

NET "testpoint_isf_ctrl(14)" TNM_NET = testpoint_isf_ctrl(14);

TIMESPEC TS_testpoint_isf_ctrl_14 = PERIOD "testpoint_isf_ctrl(14)" 27 MHz HIGH 50%;

#Created by Constraints Editor (xc3s700an-fgg484-4) - 2011/10/20

TIMEGRP "Clock_80MHz" = RISING "RegFGC3_DCM_eng_CLK2X_BUF";

TIMEGRP "ISF_clock" = FALLING "testpoint_isf_ctrl(14)";

TIMESPEC TS_ISF_eng = FROM "ISF_clock" TO "Clock_80MHz" TIG;

But then when re-running the Implementation, ISE gives me the following warnings ….

WARNING	ConstraintSystem:58 - Constraint <TIMEGRP ISF_clock = FALLING TIMEGRP "testpoint_isf_ctrl(14)";> [TOPLEVEL.pcf(1510)]: FALLING(TIMEGRP "testpoint_isf_ctrl(14)") does not match any design objects.
WARNING	ConstraintSystem:56 - Constraint <PATH TS_ISF_eng_path = FROM TIMEGRP "ISF_clock" TO TIMEGRP "Clock_80MHz";> [TOPLEVEL.pcf(1515)]: Unable to find an active 'TimeGrp' constraint named 'ISF_clock'.
WARNING	ConstraintSystem:56 - Constraint <PATH "TS_ISF_eng_path" TIG;> [TOPLEVEL.pcf(1516)]: Unable to find an active 'Path' constraint named 'TS_ISF_eng_path'.
WARNING	ConstraintSystem:80 - Constraint <PATH "TS_ISF_eng_path" TIG;> [TOPLEVEL.pcf(1516)]: This constraint will be ignored because one or more of its specified associations could not be found.
WARNING	Timing:3223 - Timing constraint PATH "TS_ISF_eng_path" TIG; ignored during timing analysis.
WARNING	Par:468 - Your design did not meet timing. The following are some suggestions to assist you to meet timing in your design. Review the timing report using Timing Analyzer (In ISE select "Post-Place & Route Static Timing Report"). Go to the failing constraint(s) and evaluate the failing paths for each constraint. Try the Design Goal and Strategies for Timing Performance(In ISE select Project -> Design Goals & Strategies) to ensure the best options are set in the tools for timing closure.
INFO	Timing:2761 - N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.

Is there something about the name of the net , with a parenthesis?

Thanks

Compiler: Synplify D2010

ISE: 13.2 Application O.61xd

[ajmirg]

Do you mean that you cannot find these two nets using Constraints Editor?

Can you try:

NET "testpoint_isf_ctrl*14*" TNM_NET = sometestpoint;

Is the net testpoint_isf_ctrl(14) clocking synchronous paths?

[jgomezco]

Hi,

The net testpoint_isf_ctrl(14) has been correctly detected by Constraint Editor as being a Clock.

            i.e, when I open it, it appears automatically when looking at Timing_constrains/Clock_Domains part, so that’s why I think it is interpreted correctly as a clock.

This net:

- is generated with a FSM

- goes to:

            - a vector signal

            - a Shift Register clock input

            - a SPI_ACCESS module (I am using a Spartan-3AN), clock input

I have tried your proposition (modifying by hand the UCF file):

1-

#Created by Constraints Editor (xc3s700an-fgg484-4) - 2011/10/20

NET "FPGA_SCIVS_MODE" TNM_NET = FPGA_SCIVS_MODE;

TIMESPEC TS_FPGA_SCIVS_MODE = PERIOD "FPGA_SCIVS_MODE" 10 MHz HIGH 50%;

NET "testpoint_isf_ctrl*14*" TNM_NET = isf_clock_name;

TIMESPEC TS_testpoint_isf_ctrl_14 = PERIOD "isf_clock_name" 27 MHz HIGH 50%;

#Created by Constraints Editor (xc3s700an-fgg484-4) - 2011/10/20

TIMEGRP "Clock_80MHz" = RISING "RegFGC3_DCM_eng_CLK2X_BUF";

TIMEGRP "ISF_clock" = FALLING "isf_clock_name";

TIMESPEC TS_ISF_eng = FROM "ISF_clock" TO "Clock_80MHz" TIG;

Result: "testpoint_isf_ctrl*14*" is not recognised as an internal net.

2- I can leave with this because Timing warnings Set-up are not real as both systems are in different clock domains … but I would like to know what happens….

I could send you the full project…

Thanks

[ajmirg]

The problem is with:

TIMEGRP "ISF_clock" = FALLING "testpoint_isf_ctrl(14)";

testpoint_isf_ctrl(14) is a group of components, which you can find either in the .pcf (make a search for it) or by Query> Timing groups. Check if there is a falling edge i.e local inversion of clock in the group of components grouped under testpoint_isf_ctrl(14). If there is none, then ISF_clock will be empty, leading to this warning.

[jgomezco · Accepted solution]

Hi,

I have found this solution:

- My system is basically a Shift Register that stores the serial data generated by the SPI_ACCESS module of a Spartan3-AN.

- The SPI_ACCESS presents the output data at the isf_clock falling edge and my Shift-register loads it at the isf_clock rising edge.

- Due to the fact that it is inside the SPI_ACCESS that the ‘inversion’ of isf_clock is done, pehaps that is the reason why it is not ‘seen’ by ISE

Solution:I have modified my VHDL to change the dudty cycle of isf_clock and the PERIOD constraint of the isf_clock: 28MHz (as before), the Duty-cycle now is 30%/70% (High/Low).

So now there is not anymore a timing warning on that part…….

It seems to me that this is a good solution …..

Thank you for your help

[endab]

I'll mark this thread as resolved based on lastest note.