I've tried some perverted stuff. Here is forwarding clock with ODDR2 and in the same time using pad as external clock source. Logically this is what I need, now possible to put nice OFFSET IN constraint. But...after this configuration started, my FPGA became self-powered on Vccint with 2.5V. Even then regulator 1.2V disabled FPGA outputs 2.4V-2.5V on Vccint. Also it's very hot, but still works in some miracle way. Code chunk:
wire wRecoverClock;
ODDR2 #(
.DDR_ALIGNMENT ("NONE"),
.INIT (1'b0),
.SRTYPE ("SYNC")
) ODDR2_U1 (
.Q (wRecoverClock), // 1-bit DDR output data
.C0 (!IP_PHY1_EFCLK), // 1-bit clock input
.C1 (IP_PHY1_EFCLK), // 1-bit clock input
.CE (1'b1), // 1-bit clock enable
.D0 (1'b1), // 1-bit data input
.D1 (1'b0), // 1-bit data input
.R (1'b0), // 1-bit reset input
.S (1'b0) // 1-bit set input
);
wire wFeedbackClock;
IOBUF IOBUF_U1 (
.O(wFeedbackClock), // Buffer output
.IO(OP_MCU_EFCLK), // Buffer inout port
.I(wRecoverClock), // Buffer input
.T(1'b0) // 3-state enable input
);
always @(posedge wFeedbackClock) // Useful stuff
...
And in UCF:
NET "OP_MCU_EFCLK" TNM_NET = MCU_RMII_CLK | CLOCK_DEDICATED_ROUTE = FALSE ;
TIMESPEC "TS_MCU_RMII_CLK" = PERIOD "MCU_RMII_CLK" 20.0 ns HIGH 12.0 ns ;
OFFSET = IN 6 ns VALID 8 ns BEFORE "OP_MCU_EFCLK" RISING ;
Seems my FPGA died right now :'-( Afraid to try this on another device. Anyone seen this before?
