Timing Analysis

[rchakraborty]

I have a question regarding the setup relationship equation in UG612

Refer UG612 on page

I am not able to understand the statement below:

How can a longer clock delay lead to smaller setup time?

My understanding is that the longer the clock delay, the longer the data has time to settle at the input of the IOB FF. The lonegr the time the data has before the clock edge, the lonegr the setup time.

For example,

if a clock with a period of 4 ns and associated data has a setup time of 1 ns at the input pins of the FPGA. If the clock delay (3 ns) is longer than the data delay (2 ns), the setup time increases to 2 ns.



I think I am making a wrong assumption somewhere. An explanation would be greatly appreciated.

Thank you

[eteam00]

Think about this again.  The setup time which is quoted is at the package pins, data relative to clock edge.  Any internal clock path delay between the package pin and the register will reduce the required data to clock setup time at the package pins.

If the data and clock arrive at the package pins simultaneously, and the path delays from package pins to the register for the clock is 20nS and for the data is 10nS, then the data arrives at the register 10nS before the clock edge.  That's a freebie 10nS setup time at the register, even though the data and clock arrived at the package pins simultaneously (0 nS setup time).

It all makes sense, just give it time...

-- Bob Elkind

[ywu]

Your understanding is correct. The statement in UG612 should be read as:

"The longer the clock path delay, the smaller the external setup time REQUIREMENT becomes". 

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rchakraborty wrote:

I have a question regarding the setup relationship equation in UG612

Refer UG612 on page

I am not able to understand the statement below:

How can a longer clock delay lead to smaller setup time?

My understanding is that the longer the clock delay, the longer the data has time to settle at the input of the IOB FF. The lonegr the time the data has before the clock edge, the lonegr the setup time.

For example,

if a clock with a period of 4 ns and associated data has a setup time of 1 ns at the input pins of the FPGA. If the clock delay (3 ns) is longer than the data delay (2 ns), the setup time increases to 2 ns.



I think I am making a wrong assumption somewhere. An explanation would be greatly appreciated.

Thank you

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