Timing Analysis

[carlxilinx]

On Figure 3-18 of page 69 of Timing Closure User Guide UG612 (v 13.4) January 18, 2012 http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/ug612.pdf,

how could the minmum hold time to be negative? I thought that the clock should strobe into the center of valid data window since it is at the IOB input *register*. If it said "IOB input pad", that would be ok to me. Did I understand it wrong?

[eteam00]

how could the minmum hold time to be negative?

Simple.

Setup and hold time are specified at the package pins for data input relative to clock input, and not at the IOB register.

Setup and hold times at the IOB register are different than the setup and hold times at the package pins, because the path delay from pin to IOB register are different for the clock and data signals.

For example, the setup and hold times at the IOB register are both 0.5nS (this is defined by the FPGA technology).  If the path delay from data input pin to IOB register is longer than the path delay from clock input pin to IOB register by 750pS, then

• required setup time at the package pins is 1.25nS (greater at the package pins than at the IOB register).
• required hold time at the package pins is -0.25nS (lesser at the package pins than at the IOB register).

-- Bob Elkind

[carlxilinx]

Hi Bob,

I agree with you on:
Setup and hold times at the IOB register are different than the setup and hold times at the package pins, because the path delay from pin to IOB register are different for the clock and data signals.

Also, I see the relationship between the Setup/Hold Time Requirement at IOB register and Setup/Hold Time Requirement at Input Pad as follows:

Setup Time Requirement at Input Pad = Data path Delay + Setup Time Requirement at IOB Register - Clock Path Delay
Hold Time Requirement at Input Pad = Clock Path Delay + Hold Time Requirement at IOB Register - Data Path Delay

However, UG612 clearly says that: Setup and Hold Times With Respect to Clock at IOB input Register. Do they have a typo here?

Thanks.

[carlxilinx]

I think that figure is for some device similar to Virtex-II Pro,

http://www.xilinx.com/support/documentation/data_sheets/ds083.pdf

So the question again is: do they really mean at IOB register or at IOB pad?

And, what does that "Pad, no delay", "Pad, with dealy" mean?

[eteam00]

However, UG612 clearly says that: Setup and Hold Times With Respect to Clock at IOB input Register. Do they have a typo here?

No, I do not think there is a typo here.  I also do not think this is a cause for concern.  UG612 is not a specification document, it is a tools user guide (one of many) for designers which applies to Xilinx development tools used for all Xilinx FPGA families.

If you seek specific setup and hold time specifications for a specific target FPGA device or device family, you need to look in the device family datasheet for the target devices.  For example:  DS162 (for Spartan-6), Table 35.

-- Bob Elkind

[carlxilinx]

Hi Bob,

While I agree that UG612 is a user guide, the illustration and explanation has to be accurate. Do you notice that they used term IOB Input *Register*, not IOB Input *Pad*. Again, How could there is a negative hold time requirement at *register* input. Yes, DS162 Table 35 no longer refer the setup time at IOB *register*, it says:

TIDOCK/TIOCKD D pin Setup/Hold with respect to CLK without Delay

I assume that the D pin is the input pad, it this correct? Thanks.

[eteam00]

While I agree that UG612 is a user guide, the illustration and explanation has to be accurate.

Has to be accurate for explaining and illustrating timing closure?  yes.

Has to be accurate setup/hold time figures for any specific FPGA?  no.

Do you have a firm foundation for believing the figures are not accurate?

Again, How could there is a negative hold time requirement at *register* input. Yes, DS162 Table 35 no longer refer the setup time at IOB *register*, it says:  TIDOCK/TIOCKD D pin Setup/Hold with respect to CLK without Delay

I assume that the D pin is the input pad, it this correct?

No, not correct.  Any setup/hold time specification for input pad must also specify the IOSTANDARDs being used for both the clock and data inputs, and also specify the clock buffer path from pin to register.  These details are missing, and logical deduction confirms that the DS162 Table 35 specifications apply to "pins" of the ILOGIC2 (internal) block which includes the input registers.

We could play this game forever.  You are exaggerating the importance of a very small, inconsequential nit.  The setup and hold time figures in UG612 will not affect your design or anyone else's design, but the timing closure lessons and instructions may greatly help your design.

It's time to move on, Carl.

-- Bob Elkind

[carlxilinx]

Hi Bob, Sorry that I am not trying to be picky. I am learning ... A timing diagram may be helpful. Thanks.

[ywu · Accepted solution]

* TIDOCK/TIOCKD D pin Setup/Hold with respect to CLK without Delay". The D pin in this statement is the D pin at the input register. Note that the "input register" in all FPGAs doesn't mean the final flip-flop that captures data. It refers to the whole IOB structure for data capture (e.g ILOGIC block in Virtex6). There is still circuit before the actual data and clock get to the final flip-flop. Using the snapshot below as an example, TIDOCK/TIOCKD is specified at the D and CLK input of the ILOGIC block. As you can see, D and CLK go through different paths to the destinaltion FF. If the D path delay is longer than the CLK path delay, you will see negative hold time requirement.

* OFFSET IN constraint is specified on the data input PAD w.r.t clock input PAD.

---

carlxilinx wrote:
Hi Bob, Sorry that I am not trying to be picky. I am learning ... A timing diagram may be helpful. Thanks.

---

[carlxilinx]

Thank you so much Jim! You have answered a question that puzzeld me for so many years. I will keep this in mind while reading Xilinx document:

Note that the "input register" in all FPGAs doesn't mean the final flip-flop that captures data. It refers to the whole IOB structure for data capture.

Also thanks for adding the figure to show the data/clock paths inside the IOB. That is very convincing and helpful.