Timing Analysis

[ramachandrans]

My module, say block1.vhd, module contains ipcore instantiations and user logic.

The clock frequency is 375MHz and it is for a signal processing application.

FPGA is Virtex 5.

And I’ve timing errors to fix. Synthesis reports timing on only the user logic, while the ipcores are treated as black box.So this doesn’t even give a rough estimate, when there is ipcore in the top level.Implementation reports timing on all the modules, including the ipcores.

But since the implementation is based on placement and my module is sub block, I cannot fully rely on the timing estimate shown by the tool.

Again when this block is to be instantiated in the top level, the timing error is going to be on a different path!! Could you suggest me if there are any guidelines to concentrate on which warning (synthesis / implementation)?

[bassman59]

Don't bother looking at the synthesis timing estimates.

[woutersj]

Yup, XST is almost always reporting timing failures on some of our designs and they pass P&R without much effort.

[deshya]

Hi, 

Can I please know how to give a clock of 100 MHz on the Virtex 5 LX110T? (http://www.hitechglobal.com/boards/v5pciexpress.htm) 
The crystal says that it is 50 MHz and even when I give 100 MHz on the timing constraints file, my code on the board runs at 50 MHz(I checked this with a counter). I m using the J16 pin, which is the oscialltor externally fixed as the clock. 
I want to know how to give a 100 MHz clock. 
I m using the board in Standalone mode and programming with the JTAG 

Thank you

Deshya

[deshya]

Hi, 

Can I please know how to give a clock of 100 MHz on the Virtex 5 LX110T? (http://www.hitechglobal.com/boards/v5pciexpress.ht m) 
The crystal says that it is 50 MHz and even when I give 100 MHz on the timing constraints file, my code on the board runs at 50 MHz(I checked this with a counter). I m using the J16 pin, which is the oscialltor externally fixed as the clock. 
I want to know how to give a 100 MHz clock. 
I m using the board in Standalone mode and programming with the JTAG 

Thank you

Deshya

[bassman59]

---

deshya wrote:

Hi, 

Can I please know how to give a clock of 100 MHz on the Virtex 5 LX110T? (http://www.hitechglobal.com/boards/v5pciexpress.ht m) 
The crystal says that it is 50 MHz and even when I give 100 MHz on the timing constraints file, my code on the board runs at 50 MHz(I checked this with a counter).

---

Uh, duh --- you feed the design a 50 MHz clock, so the design runs at 50 MHz. Why are you surprised by this?

---

I m using the J16 pin, which is the oscialltor externally fixed as the clock. 
I want to know how to give a 100 MHz clock. 
I m using the board in Standalone mode and programming with the JTAG 

---

How about: RTFM to see if this board offers a connection to an FPGA clock input pin to which you can connect a 100 MHz oscillator? Unsolder the existing 50 MHz oscillator and solder in a 100 MHz job in its place?