Timing Constraint for Multiple Clock Domains in EDK

himmeljack · ‎09-07-2011

Hi,

I have encountered a problem for several days. There are some control signals from the PLB slave registers in clock domain A, let's say, with a 125 MHz clock generated from a clock of 100 MHz through a DCM. These control signals are flags (pulses) to tell other modules in different clock domains B, C, D (for example, 40 MHz, 80 MHz, 150 MHz). I have already used synchronizers with three D-flipflops, in which first two are used as normal synchronizers to remove the metastable status and the third one to help to generate flags in other domains together with some toggle signals like in the following

--
-- Clk_A    +---+ +---+ +---+ +---+ +---+ +---+ +---+ +--
--      ---+ +---+ +---+ +---+ +---+ +---+ +---+ +---+
--
-- Flag_A      +-------+
--      -----+ +------------------------------------------------
--
-- Flag_Toggle_A +-------------------------------------------------
--     ------------+
--
-- or      ------------+
-- +-------------------------------------------------
--
-- Clk_B     +-----+ +-----+ +-----+ +-----+ +-----+
--    --- + +-----+ +-----+ +-----+ +-----+ +----
--
-- Sync(2:0)   ----------------+-----------+------------+------------+--------
--      | 000 |     001     |     011     |     111
--     ----------------+-----------+------------+------------+--------
--
-- or     -----------------+-----------+------------+-----------+---------
-- | 111 |     110 |     100 |     000
--     ----------------+-----------+------------+-----------+--------
--
-- Flag_B +----------+
--     ------------------------------------------+ +----------
--

But STILL there is a warning in EDK, which is " WARNING:Route:466 - Unusually high hold time violation detected among 52 connections. The top 20 such instances are", and the instances (connections) are of course the signals across the clock domains. After this warning report the EDK tries to work it out without end ...

Then I guess I need to constraint the clock domain like this

NET "system/Module_DCM_0_wrapper/clk_125MHz" TNM_NET = FFS "GRP_A";
NET "system/Module_DCM_0_wrapper/clk_40MHz" TNM_NET = FFS "GRP_B";
TIMESPEC TS_Example = FROM "GRP_A" TO "GRP_B" 2 ns DATAPATHONLY;

But the EDK cannot find the signals. It seems that they have wrong pathes.

The problem is how could I find the right path of the signals inside the system (in this case generated by a DCM, or a clock generator in terms of IP core) in EDK? And does this kind of timing constraint really works in clock domain crossing issue mentioned here.

Thanks in advance.

mcgett · ‎01-03-2008

Your design technique for these cross clock domain signals is correct, but the timing tools cannot automatically determine that the timing should be ignored for these paths. You need to places TIG, timing ignore,constrainton the net into the first register that you are using for metastability. The timing report should give you this net name.

------------------------------------------------------------------
Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com

austin · ‎02-27-2008

h,

Since you know what you are doing, and you want the tools to solve the problems they can solve, and ignore the ones you have already provided for; you need to use the TIMING IGNORE constraint.

Sometimes the best constraint, is to specifically ignore any constraint on ptahs, especially those between different clock domains where you have provided syhnchonizers.Given you clock names, wild-cards in the TIG(timing ignore) may take away all the problems. Iterate on the TIG commands, and check the warnings and errors in the timing report (until there are none that you have already provided for).

Austin Lesea
Principal Engineer
Xilinx San Jose

ywu · ‎11-28-2007

You can use PlanAhead to load the top level ngc and ngcs for all pcores. Once inside PlanAhead, you can easily find the clock net names in the two clock domains.

Or if you already have the timing report (.twx), open it in Timing Analyzer and then find the CDC paths. The report on those paths will tell you the source and destination clock names.

The FROM:TO constraints work for CDC paths. However, 2ns is kind of too tight.

himmeljack wrote:

Hi,

I have encountered a problem for several days. There are some control signals from the PLB slave registers in clock domain A, let's say, with a 125 MHz clock generated from a clock of 100 MHz through a DCM. These control signals are flags (pulses) to tell other modules in different clock domains B, C, D (for example, 40 MHz, 80 MHz, 150 MHz). I have already used synchronizers with three D-flipflops, in which first two are used as normal synchronizers to remove the metastable status and the third one to help to generate flags in other domains together with some toggle signals like in the following

--
-- Clk_A    +---+ +---+ +---+ +---+ +---+ +---+ +---+ +--
--      ---+ +---+ +---+ +---+ +---+ +---+ +---+ +---+
--
-- Flag_A      +-------+
--      -----+ +------------------------------------------------
--
-- Flag_Toggle_A +-------------------------------------------------
--     ------------+
--
-- or      ------------+
-- +-------------------------------------------------
--
-- Clk_B     +-----+ +-----+ +-----+ +-----+ +-----+
--    --- + +-----+ +-----+ +-----+ +-----+ +----
--
-- Sync(2:0)   ----------------+-----------+------------+------------+--------
--      | 000 |     001     |     011     |     111
--     ----------------+-----------+------------+------------+--------
--
-- or     -----------------+-----------+------------+-----------+---------
-- | 111 |     110 |     100 |     000
--     ----------------+-----------+------------+-----------+--------
--
-- Flag_B +----------+
--     ------------------------------------------+ +----------
--

But STILL there is a warning in EDK, which is " WARNING:Route:466 - Unusually high hold time violation detected among 52 connections. The top 20 such instances are", and the instances (connections) are of course the signals across the clock domains. After this warning report the EDK tries to work it out without end ...

Then I guess I need to constraint the clock domain like this

NET "system/Module_DCM_0_wrapper/clk_125MHz" TNM_NET = FFS "GRP_A";
NET "system/Module_DCM_0_wrapper/clk_40MHz" TNM_NET = FFS "GRP_B";
TIMESPEC TS_Example = FROM "GRP_A" TO "GRP_B" 2 ns DATAPATHONLY;

But the EDK cannot find the signals. It seems that they have wrong pathes.

The problem is how could I find the right path of the signals inside the system (in this case generated by a DCM, or a clock generator in terms of IP core) in EDK? And does this kind of timing constraint really works in clock domain crossing issue mentioned here.

Thanks in advance.