Timing Analysis

[rcingham]

"And I guess..."

Knowing is much better.
There's a limit to how much help I can give, as I've never used the tool flow from SysGen. If you can find the Timing Analysis Report file (.TWR), it should say which clocks and what constraints it is using. In the ISE Project Navigator flow it is fairly easuy to get it to report all unconstrained items, which is REALLY useful. Maybe that option is available to you somehow.

[ywu]

Yes, all timing constraints for SysGen blocks are derived from the "FPGA clock period" specified on the "System Generator" token. Make sure it matches the input samping period.

For decimation FIRs, even though it converts inputs from higher sample rate to lower sample rate, the DSP48s inside the FIR will operate at the higher rate and time-multiplexed with different samples to save HW resources.

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dhouibay wrote:

No I didn't constrain the other clocks but Sysgen is automatically generating the other timing regions and their constraints from the sample periods given in the Sysgen blocks. And I guess they are all derived from the global period 320MHz clock. 

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