Timing Analysis

[waris.mohammad]

Dear friends,

                         I have few doubts over TIG.

Where can i apply TIG. Kindly educate me.

I have some signals coming into FPGA. THese signals remain valid for >1clk of FPGA. Does this mean i will never face timing problems with them. 

Same for reset input. I use 2 flipflops for synchronising the reset to clock.

[nbrowdu]

You can apply a TIG directly to a NET, PIN, or INST. For example:

NET "<signal_name>" TIG;

You could even take that further. Consider a case where you wanted to apply a TIG to specific existing timing specs fanning foward from a NET:

NET "RESET" TIG=TS_fast, TS_even_faster;

You can also apply them using a FROM:TO type of constraint. For Example:

TIMESPEC TS_ DQS_UNUSED = FROM FFS TO "control_unused_dqs" TIG;

For more information, use the search function (ctrl+f) through the Constraints Guide or the Timing Closure Guide (links below).

http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/ug612.pdf

http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/cgd.pdf

[rcingham]

http://forums.xilinx.com/t5/PLD-Blog/Timing-Constraints-Part-4-of-5/ba-p/66696

[waris.mohammad]

hi rcingham,

                         Thanks for the link.

Can you plz explain how do we decide which signal is non-critical.plz.

thanks in advance.

[rcingham]

You have to understand your design fully to decide whether a particular signal is 'non-critical' with respect to timing. That sort of discernment comes with experience.

[waris.mohammad]

Dear rcingham,

                               I will appreciate if you could give an example or link for me to understand this.

regards