Timing Analysis

[zoujx2008]

Hi,

I am using the Virtex 5 to capture 10 bits data (1Gpbs), and the  differential data-ready (adc_adr, adc_adrn) is 500MHz.

The clock path and data path diagram is attached

I am not sure about how to do the constraints, so, I write the constraints as follow:

NET "adc_adr" TNM_NET = "adc_adr";
TIMESPEC TS_adc_adr = PERIOD "adc_adr" 2 ns HIGH 50%;
OFFSET = IN 0.5 ns VALID 1 ns BEFORE "adc_adr" RISING;
OFFSET = IN 0.5 ns VALID 1 ns BEFORE "adc_adr" FALLING;

adc_adr and adc_adrn are pad signals. I use the positive one to constraint, but the warning says the constraints are ingored because the "adc_adr" does not clock any registered commponets. Why? and how can I do the constraints?

thanks a lot

[ywu]

Your constraints look OK. I suggest you open a webcase to have it looked at. However, for the rate the ADC I/F is operating at, you should seriously consider using some calibration circuit for capturing the data.

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zoujx2008 wrote:

Hi,

I am using the Virtex 5 to capture 10 bits data (1Gpbs), and the  differential data-ready (adc_adr, adc_adrn) is 500MHz.

The clock path and data path diagram is attached

I am not sure about how to do the constraints, so, I write the constraints as follow:

NET "adc_adr" TNM_NET = "adc_adr";
TIMESPEC TS_adc_adr = PERIOD "adc_adr" 2 ns HIGH 50%;
OFFSET = IN 0.5 ns VALID 1 ns BEFORE "adc_adr" RISING;
OFFSET = IN 0.5 ns VALID 1 ns BEFORE "adc_adr" FALLING;

adc_adr and adc_adrn are pad signals. I use the positive one to constraint, but the warning says the constraints are ingored because the "adc_adr" does not clock any registered commponets. Why? and how can I do the constraints?

thanks a lot

---

[graces]

Please make sure the PERIOD constraint at the clock input pad is propagated to PLL outputs.

Check translate report (.bld). For a successful transformation, you should see messages like this.

TINFO:XdmHelpers:851 - TNM " adc_adr", used in period specification "TS_adc_adr", was traced
into PLL instance "my_pll". The following new TNM groups and period specifications were
generated at the PLL output(s):

[rcingham]

As noted in this thread:
http://forums.xilinx.com/t5/Implementation/IBUFGDS-to-DCM-problems/m-p/239360
it is advisable to split the IBUFGDS into an IBUFDS followed by a BUFG.

[zoujx2008]

Thank you very much.

You are so right about calibration of the data capture.

I am now so painful to do the calibration.

I am using the XC5VSX50T-1 to do the data capture in my design, For the convenience, I use the global clocking scheme for the interface clocking. But, I find it is almost impossible to do the calibration of data capture.

I am not even sure about if the global clocking can do the data capture job now. Do you have some advice?