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Timing error on memory controller clock signals
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11-02-2011 02:43 AM
Hi,
here is a part of the output copied from the console. Please have a look at this
--------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
--------------------------------------------------
* TS_SYS_CLK5 = PERIOD TIMEGRP "SYS_CLK5" 2 | MINPERIOD | -0.638ns| 0.951ns| 3| 1443
.5 ns HIGH 50% | MINLOWPULSE | 0.499ns| 2.000ns| 0| 0
--------------------------------------------------
* TS_SYS_CLK4 = PERIOD TIMEGRP "SYS_CLK4" 2 | MINPERIOD | -0.638ns| 0.951ns| 3| 1443
.5 ns HIGH 50% | MINLOWPULSE | 0.499ns| 2.000ns| 0| 0
--------------------------------------------------
* TS_instSRAM_updwn_mig_v3_4_inst_memc5_inf | SETUP | -0.240ns| 2.740ns| 4| 554
rastructure_inst_mcb_drp_clk_bufg_in = PE | HOLD | -0.008ns| | 4| 26
RIOD TIMEGRP "instSRAM_updwn_mig_v3_4_ins | | | | |
t_memc5_infrastructure_inst_mcb_drp_clk_b | | | | |
ufg_in" TS_SYS_CLK5 HIGH 50% | | | | |
--------------------------------------------------
* TS_instSRAM_updwn_mig_v3_4_inst_memc4_inf | SETUP | -0.200ns| 2.700ns| 3| 415
rastructure_inst_mcb_drp_clk_bufg_in = PE | HOLD | 0.039ns| | 0| 0
RIOD TIMEGRP "instSRAM_updwn_mig_v3_4_ins | | | | |
t_memc4_infrastructure_inst_mcb_drp_clk_b | | | | |
ufg_in" TS_SYS_CLK4 HIGH 50% | | | | |
--------------------------------------------------
* TS_instSRAM_updwn_mig_v3_4_inst_memc5_inf | MINPERIOD | -0.188ns| 0.500ns| 1| 188
rastructure_inst_clk_2x_180 = PERIOD TIME | | | | |
GRP "instSRAM_updwn_mig_v3_4_inst_memc5_i | | | | |
nfrastructure_inst_clk_2x_180" TS_SYS_CLK | | | | |
5 / 8 PHASE 0.156 ns HIGH 50% | | | | |
--------------------------------------------------
* TS_instSRAM_updwn_mig_v3_4_inst_memc5_inf | MINPERIOD | -0.188ns| 0.500ns| 1| 188
rastructure_inst_clk_2x_0 = PERIOD TIMEGR | | | | |
P "instSRAM_updwn_mig_v3_4_inst_memc5_inf | | | | |
rastructure_inst_clk_2x_0" TS_SYS_CLK5 / | | | | |
8 HIGH 50% | | | | |
--------------------------------------------------
* TS_instSRAM_updwn_mig_v3_4_inst_memc4_inf | MINPERIOD | -0.188ns| 0.500ns| 1| 188
rastructure_inst_clk_2x_180 = PERIOD TIME | | | | |
GRP "instSRAM_updwn_mig_v3_4_inst_memc4_i | | | | |
nfrastructure_inst_clk_2x_180" TS_SYS_CLK | | | | |
4 / 8 PHASE 0.156 ns HIGH 50% | | | | |
--------------------------------------------------
* TS_instSRAM_updwn_mig_v3_4_inst_memc4_inf | MINPERIOD | -0.188ns| 0.500ns| 1| 188
rastructure_inst_clk_2x_0 = PERIOD TIMEGR | | | | |
P "instSRAM_updwn_mig_v3_4_inst_memc4_inf | | | | |
rastructure_inst_clk_2x_0" TS_SYS_CLK4 / | | | | |
8 HIGH 50% | | | | |
--------------------------------------------------
TS_instSRAM_updwn_mig_v3_4_inst_memc5_inf | MINPERIOD | 2.730ns| 2.270ns| 0| 0
rastructure_inst_clk0_bufg_in = PERIOD TI | | | | |
MEGRP "instSRAM_updwn_mig_v3_4_inst_memc5 | | | | |
_infrastructure_inst_clk0_bufg_in" TS_SYS | | | | |
_CLK5 / 0.5 HIGH 50% | | | | |
--------------------------------------------------
TS_instSRAM_updwn_mig_v3_4_inst_memc4_inf | MINPERIOD | 2.730ns| 2.270ns| 0| 0
rastructure_inst_clk0_bufg_in = PERIOD TI | | | | |
MEGRP "instSRAM_updwn_mig_v3_4_inst_memc4 | | | | |
_infrastructure_inst_clk0_bufg_in" TS_SYS | | | | |
_CLK4 / 0.5 HIGH 50% | | | | |
--------------------------------------------------
Derived Constraint Report
Review Timing Report for more details on the following derived constraints.
To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
or "Run Timing Analysis" from Timing Analyzer (timingan).
Derived Constraints for TS_SYS_CLK5
+-------------------------------+-------------+---
----------+
| | Period | Actual Period | Timing Errors | Paths
Analyzed |
| Constraint | Requirement
|-------------+-------------|-------------+-------
| | | Direct | Derivative | Direct | Derivative | Direct |
Derivative |
+-------------------------------+-------------+---
----------+
|TS_SYS_CLK5 | 2.500ns| 2.000ns| 4.000ns| 3| 10| 0|
16842|
| TS_instSRAM_updwn_mig_v3_4_ins| 2.500ns| 2.740ns| N/A| 8| 0| 16842|
0|
| t_memc5_infrastructure_inst_mc| | | | | | |
|
| b_drp_clk_bufg_in | | | | | | |
|
| TS_instSRAM_updwn_mig_v3_4_ins| 0.313ns| 0.500ns| N/A| 1| 0| 0|
0|
| t_memc5_infrastructure_inst_cl| | | | | | |
|
| k_2x_180 | | | | | | |
|
| TS_instSRAM_updwn_mig_v3_4_ins| 0.313ns| 0.500ns| N/A| 1| 0| 0|
0|
| t_memc5_infrastructure_inst_cl| | | | | | |
|
| k_2x_0 | | | | | | |
|
| TS_instSRAM_updwn_mig_v3_4_ins| 5.000ns| 2.270ns| N/A| 0| 0| 0|
0|
| t_memc5_infrastructure_inst_cl| | | | | | |
|
| k0_bufg_in | | | | | | |
|
+-------------------------------+-------------+---
----------+
Derived Constraints for TS_SYS_CLK4
+-------------------------------+-------------+---
----------+
| | Period | Actual Period | Timing Errors | Paths
Analyzed |
| Constraint | Requirement
|-------------+-------------|-------------+-------
| | | Direct | Derivative | Direct | Derivative | Direct |
Derivative |
+-------------------------------+-------------+---
----------+
|TS_SYS_CLK4 | 2.500ns| 2.000ns| 4.000ns| 3| 5| 0|
16842|
| TS_instSRAM_updwn_mig_v3_4_ins| 2.500ns| 2.700ns| N/A| 3| 0| 16842|
0|
| t_memc4_infrastructure_inst_mc| | | | | | |
|
| b_drp_clk_bufg_in | | | | | | |
|
| TS_instSRAM_updwn_mig_v3_4_ins| 0.313ns| 0.500ns| N/A| 1| 0| 0|
0|
| t_memc4_infrastructure_inst_cl| | | | | | |
|
| k_2x_180 | | | | | | |
|
| TS_instSRAM_updwn_mig_v3_4_ins| 0.313ns| 0.500ns| N/A| 1| 0| 0|
0|
| t_memc4_infrastructure_inst_cl| | | | | | |
|
| k_2x_0 | | | | | | |
|
| TS_instSRAM_updwn_mig_v3_4_ins| 5.000ns| 2.270ns| N/A| 0| 0| 0|
0|
| t_memc4_infrastructure_inst_cl| | | | | | |
|
| k0_bufg_in | | | | | | |
|
+-------------------------------+-------------+---
----------+
8 constraints not met.
Mapping completed.
See MAP report file "toplevel_map.mrp" for details.
Problem encountered during the packing phase.
Design Summary
--------------
Number of errors : 1
Number of warnings : 93
In the errors tab, i saw the following:-
Pack:1653 - At least one timing constraint is impossible to meet because component delays alone exceed the constraint. A timing
constraint summary below shows the failing constraints (preceded with an Asterisk (*)). Please use the Timing Analyzer (GUI) or TRCE
(command line) with the Mapped NCD and PCF files to identify which constraints and paths are failing because of the component delays
alone. If the failing path(s) is mapped to Xilinx components as expected, consider relaxing the constraint. If it is not mapped to
components as expected, re-evaluate your HDL and how synthesis is optimizing the path. To allow the tools to bypass this error, set the
environment variable XIL_TIMING_ALLOW_IMPOSSIBLE to 1.
To set the environment variable, i used "cmd" and ran 'xtclsh' command.
Once i reached the "%" prompt, i typed in "set env(XIL_TIMING_ALLOW_IMPOSSIBLE) 1
and it sets.
still the error is there..
Re: Timing error on memory controller clock signals
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11-02-2011 08:38 AM
Perhaps rather than ignore the error you should re-architect the system? Go to a lower frequency? Solve the problem some other way?
If the tools tell you it is impossible, then there is a very good chance you are not doing something that is even reasonable to do.
Principal Engineer
Xilinx San Jose
Re: Timing error on memory controller clock signals
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11-02-2011 11:26 PM
Hi Austin Lesea,
1. my device is spartan 6 LX150T which is supposed to support datarates of 800 Mb/s for MCB (which is what i am using)
2. For a re-check, I used the project generated by MIG itself (by running that .bat file), and tried synthesizing and implementing the design ( i commented out the unwanted I/Os from mig_v_3_4.v), and still I am getting the same timing error.
(I generated MIG for a speed grade of -3, using ISE 12.4 is it because of that?, i mean the speed grade of LX150T i am going to use is -3, but as per XCN11008.pdf, earlier generated -4 speed files wil be ok for new -3 speed files, since -4 for spartan 6 was discontinued. may be that means that if i generated MCB for -3 speed grade in ISE 12.1, it means it is a lower speed grade as of now (may be -2? i donno) )
Re: Timing error on memory controller clock signals
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11-03-2011 02:30 AM
Hi,
I generated MIG core for -4 speed grade of spartan 6, and now, map, place n route got done without any glitch.. :)..
Now i am checking the same in my original design. Will get 13.2 eval today/tomorrow and then have to check for -3 speed grade in that
