Timing Analysis

[dansci]

Hi,

I have only basic experience in FPGA and never designed anything with advanced timing. Now I need something like this: I need to have clock which works first on 200 kHz and later it changes on 50 MHz. My input clock is 50MHz. Should I use two DCMs, one for divide 50MHZ by 250 to get 200 kHz and second to use later Clock Switching With Two DCMs module? Or maybe there is other simpler option?

[dansci]

Hmmm... I see Clock Switching With Two DCMs has DCMs :) So it could be enough but I also see it is impossible to divide in DCM by more than 16, but I can use dividing process. In this situation both should have CLK0 output?

[peter.lieber]

Have you looked into the BUFGMUX primitive. It allows you to multiplex different clocks and guarantees no glitches.

Also, you may be able to access the DCM coefficients from FPGA logic and change them on the fly.

[gszakacs]

Unless you are using the reduced clock speed to save power, I would suggest using

the 50 MHz clock all the time and just use a clock enable signal to switch frequencies.

The clock enable would come on for one cycle of 250 for low frequency operation, but

stay high all the time for high frequency operation.

The DCM does not have a long enough divider to generate 200 KHz.  At such a low

frequency, fabric logic is the best way to create a clock.  Another option for clock

generation using DCM + fabric would be to generate a 2x clock (100 MHz) with

a DCM and then use logic to divide that either by 2 or by 500.  The output of the

logic (must be directly from a flip-flop output to avoid glitches) would then drive

a BUFG to clock the system.

-- Gabor

[avrumw]

I would use a BUFGCE. The BUFGCE is a global clock buffer (a BUFG) with a clock enable input, which can be dynamically controlled.

You would need to use both a conventional BUFG as well as a BUFGCE, both taking in the 50MHz clock (either directly from a clock capable pin, or via a DCM). The ungated clock (from the BUFG) would control a small state machine/counter, which generates the CE for the BUFGCE. When you want the main clock to run at 200KHz, simply assert the CE on one out of every 200 clocks. When you want the main clock to run at 50MHz, leave the CE enabled all the time.

The only potential drawback is that the duty cycle of this generated (or decimated) clock is not 50/50 - at 200KHz, it would have 20ns of high time, and 4980ns of low time. As long as this clock isn't driving any negative edge FFs (which is a bad design practice), or any DDR input or output FFs, this shouldn't be a problem.

[eteam00]

When you want the main clock to run at 200KHz, simply assert the CE on one out of every 200 clocks. When you want the main clock to run at 50MHz, leave the CE enabled all the time.

The only potential drawback is that the duty cycle of this generated (or decimated) clock is not 50/50 - at 200KHz, it would have 20ns of high time, and 4980ns of low time. As long as this clock isn't driving any negative edge FFs...

Please do not muddy the distinction between CLOCK and CLOCK ENABLE.  A CLOCK ENABLE is not a CLOCK. A CLOCK ENABLE, properly used, is not applied to edge-sensitive or duty-cycle-sensitive register inputs.

-- Bob Elkind

[avrumw]

Please do not muddy the distinction between CLOCK and CLOCK ENABLE.  A CLOCK ENABLE is not a CLOCK. A CLOCK ENABLE, properly used, is not applied to edge-sensitive or duty-cycle-sensitive register inputs.

The output of the BUFGCE described above is a decimated clock; it is available on the global clock network and can directly drive the clock pins of clocked elements. If the CE to the BUFGCE is generated correctly, then the resulting clock has all the characteristics of the desired clock (50MHz or 200KHz frequencies), with the caveat of the duty cycle noted above, which does not matter to internal cells as long as only the rising edge is used (i.e. no negative edge FFs, and no DDR FFs).

Avrum

[eteam00]

Avrum,

If you are suggesting that a clock enable should be generated with a BUFGCE, and such a clock enable can easily be used (also) as a clock, you are giving extraordinarily bad advice to inexperienced user dansci and anyone else reading this thread.

The entire point of generating a low-rate clock enable is to avoid the power cost, complexities, and timing hasards of multi-clock design.

If you want to recommend a multi-clock design, then do so in plain terms with due consideration to the clock-domain crossing complexities, design verification practices, etc. for the benefit of the inexperienced users and readers.

-- Bob Elkind

[avrumw]

Bob,

I am suggesting using a BUFGE for its intended purpose - generating a gated clock. When implemented as described above, the output of the BUFGE is a proper decimated clock, and can be used as a clock. This is a legal, documented, and properly implemented clocking structure for this problem.

The output of the BUFGE is NOT a clock enable; the CE input to the BUFGCE is a clock enable that generates a gated clock. The gated clock is distributed on the global clock network and is in phase (i.e. has no skew) with the non-decimated clock available on the regular BUFG. Since is only transitions at 200KHz, it has all the power savings of any other clock at this frequency.

Please refer to the Xilinx user's guide for the proper use of the BUFGE.

Avrum

[eteam00]

Avrum,

Thank you for the clarification.  You are entirely correct in your description of the BUFGCE.  I misunderstood the intent of your suggestions (in post #5).

For the benefits of the original poster and other readers, what do you see as the advantages and disadvantages of your design approach compared to Gabor's approach (see post #4 in this thread)?

In both design approaches, a 200KHz-rate single-cycle pulse is generated from the 50MHz system clock.  From there, the two approaches diverge.

-- Bob Elkind