Timing Analysis

[dansci]

Thanks for explanation. Now it works. I replaced BUFG with BUFGMUX and removed 'divide' signal from sensitivity list. I'm using Spartan3. External clock signal comes through GCLK pin.

I have two more questions:

1. I see on oscilloscope (with 200 MHz BW) this 50 MHz clock. It never shows that clock is steady 50 MHz. It shows that clock frequency fluctuates between 49 - 51 MHz. I have device working with max frequency = 50 MHz so I can expect that there will be troubles with over 50 MHz clock. Should I be worried or it's just because of measuring so high frequency on my oscilloscope which can't show it correctly. If not, what can I do?

2. Also I see that clock peak-peak is low -> about 1.2 V (from 1.3 to 2.5 V). Will it work?

[gszakacs]

Are you looking at the clock where it goes into the FPGA?

What is generating the clock?  A crystal oscillator?

I would normally assume that a crystal oscillator has a frequency very close

to the nominal frequency.  +/- 1 MHz is probably a measurement error in the

scope.  Most oscilloscopes measure the period of the waveform and invert

it to show the frequency.  You will get your best reading when you see exactly

one cycle of the waveform on the screen.  Still, depending on the scope timebase

and whether you have repetitive sampling turned on, the measurement

resolution can be quite crude.

The amplitude of the clock signal worries me more than the frequency reading.

Are you sure that the scope bandwidth is 200 MHz?  Many scopes have a

setting to reduce the bandwidth when looking at lower frequency signals.

If this is on, then your clock will not only look like it has lower amplitude, but

it will also look a lot like a sine wave.

-- Gabor

[dansci]

I'm looking at clock from BUFGCE (clkOutBufgce), simply moved out: 'clk_out <= clkOutBufgce;'. Clock is generated by crystal oscillator. My oscilloscope is Tektronix TDS2024. Bandwidth Limit is OFF. And this clock looks like a sine wave.

[rcingham]

Are you using a X10 probe?
Is the scope in high-impedence mode?
Measure between the oscillator and FPGA.

[bassman59]

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dansci wrote:

I'm looking at clock from BUFGCE (clkOutBufgce), simply moved out: 'clk_out <= clkOutBufgce;'. Clock is generated by crystal oscillator. My oscilloscope is Tektronix TDS2024. Bandwidth Limit is OFF. And this clock looks like a sine wave.

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A 200 MHz 'scope isn't fast enough to show a 50 MHz square wave as square. 

[rcingham]

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bassman59 wrote:

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dansci wrote:

I'm looking at clock from BUFGCE (clkOutBufgce), simply moved out: 'clk_out <= clkOutBufgce;'. Clock is generated by crystal oscillator. My oscilloscope is Tektronix TDS2024. Bandwidth Limit is OFF. And this clock looks like a sine wave.

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A 200 MHz 'scope isn't fast enough to show a 50 MHz square wave as square. 

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Very true. It will only get the 3rd harmonic.

You would expect a decent shape from a 'scope with 500MHz analogue bandwidth.

[gszakacs]

The TDS2024 is listed as 200 MHz bandwidth on the Tek website.  That's enough to pick up

the third harmonic of 50 MHz but not the 5th.  I would think the wave wouldn't look quite sinusoidal

at that bandwidth, but certainly not square either.  In any case, if the frequency coming out of

the FPGA matches the expected frequency, then I would imagine the input clock is running

sufficiently well to drive the FPGA input buffer.

- Gabor