Timing Analysis

[adrian.h]

Came across an unconstrained path of type PAD to OTHER.

TRCE 13.2 targetting a Virtex 5.

================================================================================
Timing constraint: Unconstrained path analysis

 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Maximum delay is  -0.076ns.
--------------------------------------------------------------------------------
Delay:                  -0.076ns (data path)
  Source:               XI_FPGA_33M_CLK (PAD)
  Destination:          fpga_blks_inst/I_COMMON/pci9056_if_inst/cpci_core/flb_comp/standard_regs/die_monitor/monitor_blk (OTHER)
  Data Path Delay:      -0.076ns (Levels of Logic = 3)

  Maximum Data Path: XI_FPGA_33M_CLK to fpga_blks_inst/I_COMMON/pci9056_if_inst/cpci_core/flb_comp/standard_regs/die_monitor/monitor_blk
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    AF20.I               Tiopi                 0.866   XI_FPGA_33M_CLK
                                                       XI_FPGA_33M_CLK
                                                       fpga_blks_inst/i_clock_reset_gen/i_clk_ibufg
    DCM_ADV_X0Y0.CLKIN   net (fanout=6)        1.028   fpga_blks_inst/i_clock_reset_gen/DCM_CLKIN
    DCM_ADV_X0Y0.CLK0    Tdmcko_CLK           -5.488   fpga_blks_inst/i_clock_reset_gen/i_dcm_fpga
                                                       fpga_blks_inst/i_clock_reset_gen/i_dcm_fpga
    BUFGCTRL_X0Y1.I0     net (fanout=1)        1.655   fpga_blks_inst/i_clock_reset_gen/CLK0_FPGA
    BUFGCTRL_X0Y1.O      Tbgcko_O              0.250   fpga_blks_inst/i_clock_reset_gen/i_clk_fpga_bufg
                                                       fpga_blks_inst/i_clock_reset_gen/i_clk_fpga_bufg
    SYSMON_X0Y0.DCLK     net (fanout=1298)     1.613   fpga_blks_inst/CLK_FPGA
    -------------------------------------------------  ---------------------------
    Total                                     -0.076ns (-4.372ns logic, 4.296ns route)

--------------------------------------------------------------------------------

The destination is system monitor who's values I am allowing the system processor to read over the cPCI interface which runs of the XI_FPGA_33M_CLK (33MHz clock) domain.

Can anyone suggest how I could constrain this PAD to OTHERS path? I can't seem to find referece to OTHERS in the constraints user guide.

[rcingham]

Is there a PERIOD constraint on XI_FPGA_33M_CLK?
Is there a (possibly derived) constraint on fpga_blks_inst/CLK_FPGA?

[adrian.h]

Yes:

NET "XI_FPGA_33M_CLK" TNM_NET = "XI_FPGA_33M_CLK";

TIMESPEC TS_XI_FPGA_33M_CLK = PERIOD "XI_FPGA_33M_CLK" 33 MHZ HIGH 50 %;

and, I think so:

Derived Constraint Report
Review Timing Report for more details on the following derived constraints.
To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
or "Run Timing Analysis" from Timing Analyzer (timingan).
Derived Constraints for TS_XI_FPGA_33M_CLK
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_XI_FPGA_33M_CLK             |     30.303ns|     10.000ns|     27.012ns|            0|            0|            5|       151445|
| TS_fpga_blks_inst_i_clock_rese|     30.303ns|     16.935ns|          N/A|            0|            0|       141724|            0|
| t_gen_CLK0_FPGA               |             |             |             |             |             |             |             |
| TS_fpga_blks_inst_i_clock_rese|      7.576ns|      6.753ns|      6.662ns|            0|            0|         9679|           42|
| t_gen_CLKFX                   |             |             |             |             |             |             |             |
|  TS_fpga_blks_inst_i_clock_res|      3.788ns|      3.331ns|          N/A|            0|            0|           42|            0|
|  et_gen_CLK2X_264             |             |             |             |             |             |             |             |
|  TS_fpga_blks_inst_i_clock_res|      7.576ns|      2.400ns|          N/A|            0|            0|            0|            0|
|  et_gen_SRAM_CLK              |             |             |             |             |             |             |             |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

TS_fpga_blks_inst_i_clock_reset_gen_CLK0_FPGA

is the derived timespec for

fpga_blks/CLK_FPGA

I think........?

[rcingham]

That table might be understandable if you can change the font to Courier...

[adrian.h]

Ok, let's try that:

Derived Constraint Report
Review Timing Report for more details on the following derived constraints.
To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
or "Run Timing Analysis" from Timing Analyzer (timingan).
Derived Constraints for TS_XI_FPGA_33M_CLK
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_XI_FPGA_33M_CLK             |     30.303ns|     10.000ns|     27.012ns|            0|            0|            5|       151445|
| TS_fpga_blks_inst_i_clock_rese|     30.303ns|     16.935ns|          N/A|            0|            0|       141724|            0|
| t_gen_CLK0_FPGA               |             |             |             |             |             |             |             |
| TS_fpga_blks_inst_i_clock_rese|      7.576ns|      6.753ns|      6.662ns|            0|            0|         9679|           42|
| t_gen_CLKFX                   |             |             |             |             |             |             |             |
|  TS_fpga_blks_inst_i_clock_res|      3.788ns|      3.331ns|          N/A|            0|            0|           42|            0|
|  et_gen_CLK2X_264             |             |             |             |             |             |             |             |
|  TS_fpga_blks_inst_i_clock_res|      7.576ns|      2.400ns|          N/A|            0|            0|            0|            0|
|  et_gen_SRAM_CLK              |             |             |             |             |             |             |             |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+