Timing Analysis

[james.o.clay@lmco.com]

I have two different clocks that are derived, via a DCM, from a single clock.  Thus, the ISE tools "know" their relative frequencies and phases.  There are a few signals that cross from one clock domain to another and, for reasons that I don't want to get into, it doesn't matter how long it takes for the signals to get from one register to another.

The problem is that I get timing errors because one of the derived clocks is 60 MHz and the other is 100 MHz, so I guess the math works out that the worst case clock offset is 3.33 ns.  I have tried setting TIG's for the nets in question but they don't seem to help- perhaps because the problematic timing constraints are not in my UCF file, they are embedded in the tools and/or the CoreGen DCM.

How can I tell the tools to ignore the cross-over between clock domains?  I can, if need be, use separate clocks and DCM's to generate the two clocks that I need, but I would rather not do that for power consumption reasons (assuming once DCM uses less power than two).

Thanks for your help.

[gszakacs]

The normal way to handle cross-clock-domain paths is to define a

time group for each clock net and then use TIG constraints or

FROM : TO time constraints with an easily achievable setting.

For example:

NET "derived_60M_clk" TNM_NET = clk_60M_grp ;

NET "derived_100M_clk" TNM_NET = clk_100M_grp ;

TS_Ignore_60M_to_100M = FROM clk_60M_grp TO clk_100M_grp 16 ns DATAPATHONLY;

TS_Ignore_100M_to_60M = FROM clk_100M_grp TO clk_60M_grp 16 ns DATAPATHONLY;

The "derived_xxx_clk" names should match your global clock net names on the output of the DCM.

-- Gabor

[james.o.clay@lmco.com]

Thanks, I'll try that.

[james.o.clay@lmco.com · Accepted solution]

Just wanted to record for posterity's sake that this didn't work, though I still appreciate the suggestion.  I apologize that I didn't record the error message.  It was something about the FROM/TO constraint only applying to design:net, design:pin, and something else.  I thought that meant that I got the net names wrong, but I tried various names that should have worked, including wildcards and using the exact net names in the derived constraints in the Constraints Editor.

I then took the path of least resistance and used two DCMs and two different source clocks to produce the two clocks.  Hopefully this won't be much of a power hit.