03-07-2012 08:08 AM
No, D matches the phase on the output of the IBUFG (A), and C matches the input to the IBUFG taking into account the skew external, and the DFF delay.
The output D is system synchronous design, the output C is source synchronous design. Remember that the output phase at the DCM is made the same as the phase coming into the CLKFB pin (CLKIN-CLKFB is forced to zero).
Xilinx San Jose
03-07-2012 08:33 AM
1. "C matches the input to the IBUFG taking into account the skew external, and the DFF delay."
Did you mean upper IBUFG?
2. If " (CLKIN-CLKFB is forced to zero)" then:
D matches A,
A matches E,
so: D matches E what actually was my question in 1st post. Please confirm that D matches E.
03-07-2012 08:59 AM
Nope. Read through my post, again. The feedback internally is different that the feedback externally, so the two outputs must be different.
google source vs system synchronous xilinx
Lots of good app notes, etc. out there to explain this.
Xilinx San Jose
03-07-2012 09:53 AM - edited 03-07-2012 09:54 AM
It seems to me that there is a contradiction between your statement and documentation (ug070.pdf). You wrote that "output D is system synchronous design" and "D matches the phase on the output of the IBUFG (A)".
On the other hand the pdf says that if DCM's DESKEW_ADJUST=SYSTEM_SYNCHRONOUS then the DCM adds extra delay to the feedback path to compensate delay introduced by IBUFG. In that case:
- "D matches the phase on the output of the IBUFG (A)" - is not correct, but
- D matches the phase on the input of the IBUFG is correct. Please comment.
06-28-2012 07:16 AM
Is there any updates after so many month?
I am facing a similar situation now, the difference is I am targeting Spartan 3E rather than v4/5, I used Architecture Wizrad in ISE 10.1 to generate the 2 DCM structure (option "Board Deskew with An Internal Deskew"), in the auto generated ucf file both dcm has DESKEW_ADJUST = SYSTEM_SYNCHRONOUS, so under this condition , is D phase aligned with E?