Timing Analysis

[shyking]

There is a hold timing failure between register to BRAM, the source register is close to the BRAM, so the data path delay is very small(0.052ns) ,but the BRAM Trckd is bigger than the data path delay (0.503ns), so the hold timing can't close. how can i resolve this problem ? thanks!

[smarell]

The slack(hold) formula is

slack(hold)=requirement - (clock path skew + uncertainty - data path)

Hence, by reducing the clock path delay, you will be able to close the timing.

[muthyam]

Delaying the clock is the best method to meet the hold requirement.

[sampatd]

Can you post the timing report of the path that is failing hold?

Thanks.