Warning:No Top-level Input clock for the design

leshuocheng · ‎07-19-2011

In my design ,when adding chipscope to my design ,compiling will appear this problem:

ERROR: 1 constraint not met.

PAR could not meet all timing constraints. A bitstream will not be generated.

To disable the PAR timing check:

1> Disable the "Treat timing closure failure as error" option from the Project Options dialog in XPS.

OR

2> Type following at the XPS prompt:
XPS% xset enable_par_timing_error 0
********************************************************************************
make: *** [implementation/system.bit] 错误 1
Done!
WARNING:EDK:1954 - No Top-level Input clock for the design.

Deleting the chipscope ,this problem is disappeared.But still exist the WARNING.

I want to know why ,how can I solve this problem?

Thanks for your replay!

sushantm · ‎04-02-2011

Hi,

It seems you setup and hold timings are not close hence dosent meet.

There is a option in XPS settings by default it is enable you have to disable to"treat timing closure as an error".

Then it will not show the error but can may give the warning.

--Sushant Mahajan
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