Timing Analysis

[shreyassg13@gmail.com]

Hello All,

I have written a verilog code which says that my maximum frequency is around 17 MHz. But I have used the same code with an onboard clock of 50 MHz and it worked fine. So what does this mean? Are we not supposed to use higher frequency than the one in log report or sometimes it works with higher frequency? Any suggestions would be helpful.

And one more thing: the log report said maximum frequency of 17 MHz but in my code I am generating 150 MHz using DCM and 50 MHz on board clock. And it worked fine. Please throe some light on as to what should be the clock used while implementing on hardware?

[rcingham]

Which 'log report'?

[shreyassg13@gmail.com]

When I generate the programming file, in the console I see the term maximum frequency. It is under final report, clock information. Is there any other place where  I should look for it?

[rcingham]

Can you post that part of the console output here? (Use copy+paste).

Have you set any timing (period/frequency) constraints?

[shreyassg13@gmail.com]

Hello,

I have attached the report because it is too long to fit here.

[rcingham]

That is the Synthesis timing estimate, which is notoriously unreliable.
http://forums.xilinx.com/t5/Synthesis/Synthesis-Timing-Estimate-considered-harmful/m-p/214413

So, it doesn't really mean anything, and should be ignored.

Meaningful timing information is output by the TRCE programme ("Generate Post-Place & Route Static Timing").
Look in the .TWR file for its output, or click the 'Timing Report' link in PN.

[shreyassg13@gmail.com]

In the timing report, what should I search for? I see

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |   59.124|         |         |         |
---------------+---------+---------+---------+---------+
 

Is that it? even then it is 59.124 ns or 16.9MHz. But I have used a higher frequency and it worked.

[rcingham]

Have you set a PERIOD constraint on your clock(s)?

[shreyassg13@gmail.com]

I dont know what u r talking about. I have not set any constraint. Where can I know about these settings or constraints you told?

[rcingham]

You set the constraints in the UCF file (and optionally in the XCF file).

Read The Fine Constraints Guide (usually cgd.pdf), looking for the section on PERIOD constraints.

As it's POETSday today, I'm in a good mood, so here's an example:
NET "clk32" TNM_NET = clk32;
TIMESPEC TS_clk32 = PERIOD "clk32" 31.25 ns HIGH 50%;