Timing Analysis

[danbo.liang]

In my project, I encounter a component switching limits as below.

Device:XC6VLX550T ISE version:13.4

My question:

1 What is the reason why generate thiscompoent switching limits?

2 Is there any effect on my design if it is not resloved?

3 How to reslove it?

My timing constraints are below:

NET "xrtc_osc_i" TNM_NET = xrtc_osc_i;
TIMESPEC TS_xrtc_osc_i = PERIOD "xrtc_osc_i" 30 us HIGH 50%;

[danbo.liang]

In my project, I encounter a component switching limits as below.

Device:XC6VLX550T ISE version:13.4

My question:

1 What is the reason why generate thiscompoent switching limits?

2 Is there any effect on my design if it is not resloved?

3 How to reslove it?

My timing constraints are below:

NET "xrtc_osc_i" TNM_NET = xrtc_osc_i;
TIMESPEC TS_xrtc_osc_i = PERIOD "xrtc_osc_i" 30 us HIGH 50%;

[austin]

d,

Perhaps the frequency is too low for the MMCM, or some other element connected to the global clock of 1 MHz?

MMCM minimum frequency in is 10 MHz.

http://www.xilinx.com/support/documentation/data_sheets/ds152.pdf

page 52....

[danbo.liang]

Dear austin,

Thanks your relay.

"xrtc_osc_i" is a IO pad which is connected through a global clock pin.

It is not related with MMCM at all.

From timing report, the limit comes from the BUFGCTRL(Tbcper_I), but I didn't find anyting about the max period limit in the ds152.pdf

Another question: what does the paramter "Tbcper_I" mean?

Thanks your help!!!

[austin]

d,

Without going through the manual for your part, I suspect that there are timing constraints on the control pins for the BUFGMUX element.

If your are switching between two clocks, it may be the tools don't like something about the control signals.

Try using a simple BUFG instead and see if the warning goes away.

Or, it may be a bug in the software (although I haven't heard of such a thing).

What part family?

[chrisz]

The "Tbcper_I" means:

 "bc" => BufgCtrl

 "per_I" => Period Limit

All major components in the FPGA have a component switching limit, which is a min or max frequency that the element can operate at with out failing.

[danbo.liang]

Dear austin.lesea,

Family: Virtex6

Device: XC6VLX550T

Package: FF1760

Speed: -2

There is no switching on the BUFGCTRL, just only one signal "xrtc_osc_i" input

Pin constraint is below, the pin is a global clock pin

NET "xrtc_osc_i"   LOC = "AH11 ";  #AH11 IO_L0P_GC_34 OSC_OUT2 I/O clk

[danbo.liang]

Dear Zehc,

That means the BufgCtrl has the max period limit.

Why is there this limit about BufgCtrl?

If my period beyond the max period limit, will there be any wrong?

[austin]

All,

There is no min period for the fabric (BUFG, CLB, LUT, DFF, IOB, etc...).

Generally, everything works right down to DC.  There are elements light the MMCM, and the IOSERDES, MGT's, ADC, that have frequency limits.

I have no idea why it should, or would complain about anything below 1 MHz on a clock just clocking logic....

I would report it as a bug.

[chrisz]

The majority of the fabric elements have a min period or max frequency limit in the speed files.  Many of the same elements also have a max period or min frequency limits too. 

Please open a webcase and Technical Support can investigate this issue.  Please provide a testcase, so we can reproduce the issue.

[danbo.liang]

Dear All,

Any progress???