Timing Analysis

[dk_k]

Hi all,

The OFFSET constraint does not optimize paths clocked by an internally generated clock.

We have an external input clock of 50 Mhz, which is divided by a DCM internally to generate a 25 Mhz clock. The internal logic works with 25Mhz clock.

How do we apply the OFFSET constraints?

If our requirement is 10 ns AFTER 25 Mhz clock RISING, then with respect to the 50Mhz what should be the value that has to be applied ? 20 ns ? 5 ns ?

Thanks

dkk

[endab]

Hello Dkk,

You should apply the OFFSET IN constraint so that it describes the relationship between the clock and data arriving at the FPGA. The OFFSET constraint covers the data path between a PAD and input FF. The tools will then use the data path information inside the device and the clock path information (including any clock modifying blocks, DCMs, MMCMs, BUFGs etc….) to report the setup and hold information at the FF.

There must be a PERIOD constraint on the clock at the PAD so the tools can understand the clock path and any phase adjustments or multiplication / division on the clock.

You can find more information on this on page 14 of the Timing Closure User Guide, UG612:

http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_4/ug612.pdf

Thanks

[dk_k]

Thanks for the reply.

I have gone through UG612, from page -54.

For example, the internal clock is a divide by two version of the external clock,
and the original requirement of the OFFSET OUT with the internal clock was 10
ns, then the requirement of the OFFSET OUT with the external clock is 20 ns.

We have an external input clock of 50 Mhz, which is divided by a DCM internally to generate a 25 Mhz clock. The internal logic works with 25Mhz clock.

Our output constraint requirement is 10 ns AFTER 25 Mhz clock RISING, then according to UG612, the output constraint w.r.t. 50 Mhz clock should  be 20 ns. Is it ok ?

Thanks

dkk