Timing Analysis

[solarwafer]

when par done sucessful

par report(mydesign.par) said there are 8719's load on clk_bus.

but twr report(mydesign.twr) said " clk_bus,  there are 0 path analyzed"

ISE version is 13.2 on linux platform.

can anyone tell me why

[austin]

s,

No paths analyzed may mean that it found no constraints to apply.

I would apply the simplest PERIOD constraint to that clock, and try again.

[austin]

Also,

"If the design has two PERIOD constraints that cover the same paths, the later PERIOD constaint in the PCF file covers or analyzes these paths. The previous PERIOD constraints show 0 items analyzed in the timing report. In order to force the timing analysis tools to use the previous PERIOD constraints, instead of the later one, use the PRIORITY keyword on the PERIOD constraints. In addition to the PRIORITY keyword, a multi-cycle or FROM:TO constraint can be used to cover these paths."

[chrisz]

If 'clk_bus' drives an MMCM/PLL, then the static timing analysis will report 0 paths analyzed.  This clock wire does not drive any synchronous elements.  The post MMCM/PLL wire/nets drive the majority of the logic in the design.  Please review the post MMCM/PLL PERIOD constriants for the correct analysis of your design.