ISE version is 10.1. The device is xc5vfx70t-2ff1136.
Error message as follows:
timing constraint: NET "tile0_rxusrclk0_i" PERIOD = 4 ns HIGH 50%;
191 paths analyzed, 146 endpoints analyzed, 2 failing endpoints
2 timing errors detected. (2 setup errors, 0 hold errors)
Minimum period is 4.104ns.
--------------------------------------------------------------------------------
Slack: -0.104ns (requirement - (data path - clock path skew + uncertainty))
Source: inst_mydesign/tile0_mydesign_i/gtx_dual_i (HSIO)
Destination: inst_dff1/Qout_0 (FF)
Requirement: 4.000ns
Data Path Delay: 4.069ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns
Source Clock: tile0_rxusrclk0_i rising at 0.000ns
Destination Clock: tile0_rxusrclk0_i rising at 4.000ns
Clock Uncertainty: 0.035ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path: inst_mydesign/tile0_mydesign_i/gtx_dual_i to inst_dff1/Qout_0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
--------------------------------------------------- -------------------
GTX_DUAL_X0Y3.RXDATA00 Tgtxcko_RXDATA 1.433 inst_mydesign/tile0_mydesign_i/gtx_dual_i
inst_mydesign/tile0_mydesign_i/gtx_dual_i
OLOGIC_X1Y127.D1 net (fanout=1) 2.284 tile0_rxdata0_i<0>
OLOGIC_X1Y127.CLK Todck 0.352 inst_dff1/Qout<0>
inst_dff1/Qout_0
--------------------------------------------------- ---------------------------
Total 4.069ns (1.785ns logic, 2.284ns route)
(43.9% logic, 56.1% route)
The clock "tile0_rxusrclk0_i" is internal clock,a recovery clock .
Thanks !
