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Timing Analysis

Newbie

Posts: 4

Registered: ‎04-09-2009

why if I use the same internel clock for create two outputs clock with different frequency one clock of that two outputs move

‎04-09-2009 12:58 AM

Hello

I want to create two outputs clock from the same internal clock of the FPGA (virtex-4, xc4vsx35), with different frequency

the problem is that one signal from that two clocks move, one fix and the other move

can you please tell me what is the problem

you can find the code attached

thanks

best regards

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