How would one best judge when it is acceptable to generate a clock from the outputs of an internal register instead of using the standard blocks such as DCM's? My design will go onto an XC2V8000-5 part, and I'd like to use registers to generate up to a 10MHz clock if that is alright. Any information would certainly be appreciated. I am basically trying to save DCM's for the low frequency clocks if possible.
10 Mhz you could probably get a way with. It also highly depends on what you are trying to do with it. Some of the DCMs will not even create a clock at 10Mhz. If what you are using this clock for is not highly dependent on low jitter clock (which im assuming is not going to be an issue at 10Mhz) then you should be ok. But as far as official guidelines, im not sure if there are any. And would you be taking a faster clock and dividing it down?
My basic requirements are to generate the following output clocks from a single 40MHz input clock: 1. 40MHz 2. 80MHz 3. 80, 40, 20, 10, 5, or 2.5MHz based on 3-bit select 4. 120, 60, 30, 15, 7.5, or 3.75MHz based on 3-bit select
The selectable clocks are always in pairs such as 80/120, 40/60, 20/30, etc. I was thinking that I could probably get away with saving some DCM's by using registers, but I'm beginning to think it may not be the best solution. I should be able to generate all the clocks I need with a total of 4 DCM's, and the part has 12 total so I think I should be ok. The main thing I'm worried about are the quadrant rules associated with global clock buffers in these parts. I was thinking about doing a 6:1 MUX using standard logic for each of the selectable clocks and taking the MUX output to a BUFG.
Yea, i think your right. For your applications using registers is going to give you more problems then solving them. For the most part I would also think that they would not work either. DCM's are what you will have to use. In regards to crossing global clock domains, you should not have a problem i dont think. It should work out.
