Virtex® Family FPGAs

[sai.kilambi]

I am designing a source syncrhonous system in which data is forwarded from FPGA to another along with a clock. On the RX FPGA, the clock is fed to a BUFIO as well as a BUFR. I will use the BUFIO output to clock in the data and the BUFR to drive an MMCM. My question is do I need to do a clock domain crossover from the BUFIO to BUFR domain or can I consider these clocks to be synchronous.

Sai.

[eteam00]

Two approaches to take:

1. Use the MMCM to phase-align the MMCM-generated output clock to the source input clock.  You do not specify which FPGA family you are using, but the Xilinx docs generally describe this configuration as 'zero-delay-clock-buffer' mode.  If you use this approach, you probably do not need two separate clock distribution systems -- use the MMCM output for both fabric and input registers, instead of using the BUFIO copy of the clock for the input resgiters.

2.  If you are concerned about skew between the BUFIO clock and the fabric clock, you can use opposite clock edges for the input registers and the first rank of fabric registers (e.g. posedge for input registers, negedge for first rank of fabric registers, and posedge for downstream fabric registers).  This only works if the clock period is long enough and the clock skew between the two copies of the clock is small enough.

You are correct in being concerned.  Clock skew can be a fatal problem at any clock frequency, if mis-managed or ignored.

-- Bob Elkind

[sai.kilambi]

Thanks for the reply Bob. 

Sorry for not specifying the FPGA type. I am using a V6 SX475. I think I will go with option 1. BTW, will the tools pack the input registers into the IOBs if I use the MMCM output?

Out of curiosity, if I can always just use the MMCM to clock in the data why do I need a BUFIO? I mean for bringing in any data into the FPGA logic I will need to use an MMCM clockoutput or a BUFR clock output anyways. So why even bother with BUFIO.

Regards,

Sai.

[eteam00]

will the tools pack the input registers into the IOBs if I use the MMCM output?

You can direct the mapper in a number of ways.

• XST process property (in ISE shell Process window, select Synthesize - XST process, right-click, select "process properties", then select option for Pack I/O Registers into IOBs).

• MAP process property (in ISE shell Process window, select MAP process, right-click, select "process properties", then -- under Xilinx Specific Options -- select option for Pack I/O Registers/Latches into IOBs).

• .UCF / .NCF constraint

• Verilog/VHDL/Schematic constraint

See Constaints Guide UG625 IOB section (in version 13.4, this begins on page 125).

if I can always just use the MMCM to clock in the data why do I need a BUFIO?

You don't.  You would keep the BUFIO only if you wanted to avoid using a MMCM, and the skew and delay of a BUFR or BUFG is too great for your purposes.

I mean for bringing in any data into the FPGA logic I will need to use an MMCM clockoutput or a BUFR clock output anyways. So why even bother with BUFIO.

I'm not a Virtex-6 expert, but I believe BUFR and BUFG have lower frequency limits and higher skew and delay properties than a BUFIO.  In some applications, BUFIO is required for timing margin reasons.

-- Bob Elkind

[ywu]

Since BUFIO and BUFR are driven by the same clock input, they are synchronous. I assume you're also using ISERDES. If that's the case, BUFIO and BUFR combination is one of the recommeded methods for driving CLK and CLKDIV of ISERDES (see snapshot below):

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sai.kilambi wrote:

I am designing a source syncrhonous system in which data is forwarded from FPGA to another along with a clock. On the RX FPGA, the clock is fed to a BUFIO as well as a BUFR. I will use the BUFIO output to clock in the data and the BUFR to drive an MMCM. My question is do I need to do a clock domain crossover from the BUFIO to BUFR domain or can I consider these clocks to be synchronous.

Sai.

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[ywu]

BUFIO is designed for really high speed source synchronous interfaces. The IO clock tree has much smaller clock skew and duty cycle distortion than the global clock tree.

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sai.kilambi wrote:

Thanks for the reply Bob. 

Sorry for not specifying the FPGA type. I am using a V6 SX475. I think I will go with option 1. BTW, will the tools pack the input registers into the IOBs if I use the MMCM output?

Out of curiosity, if I can always just use the MMCM to clock in the data why do I need a BUFIO? I mean for bringing in any data into the FPGA logic I will need to use an MMCM clockoutput or a BUFR clock output anyways. So why even bother with BUFIO.

Regards,

Sai.

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[eteam00]

Too many IFs, WHENs, and WHATEVERs.  Original post mentioned nothing about frequency or ISERDES, and very little about application.  Sometimes the small number of details is an indication of an informed designer asking a specific, narrowly focused question.  More often, in these forums, the sparseness of detail is an indication of inexperience.

The clocking facilities in Xilinx FPGAs are quite complex and flexible, able to handle a broad range of applications.  Without specific details, no-one can affirmatively proscribe a single correct solution.  The advice I offered you might be completely correct, or completely mistaken.

Jim Wu (user ywu) knows as much about Xilinx FPGA clocking resources as anyone else on the planet -- with a few exceptions.  Even someone as knowledgeable as Jim Wu needs enough design details to provide definitive recommendations.

Sai,  if you think you need to provide more design details so that you can be given more specific design recommendations, this is a good time to make your needs clear.

Start by describing the FPGA logic generating the source synchronous interface.

• Bit rate per data channel
• Number of data channels
• Clock frequency
• Signal levels (differential or single-ended, logic standard)
• Specific implementation of the output circuit (e.g. using OBUF, IOB register, OSERDES, or ODDR?)

For your receiver, please describe

• Primary system clock frequency
• number of clocks in your design, and their purposes

Has circuit board already been designed?

Are both TX and RX FPGAs on the same board?  If not, how are they connected?

-- Bob Elkind

[sai.kilambi]

Hi Bob/Jim,

First please let me thank you for taking time and care to answer my questions.

My application does not use serdes. We already have the board. What I have are two FPGAs (both V6 SX475) and I need to send some data along with a clock from one FPGA to the other. To be specific, the data is a 32bit bus (data, address, and control signals) sent DDR with a clock (160 MHz). The data is sent differential over LVDS technology. On the receiver side I just need to clock in this data (using IDDR) and then store it into a BRAM. The logic on the receiver FPGA will take in data from the other BRAM port. This logic also runs at 160 MHz. My problem was that if I clock in the data using a BUFIO clock then to bring it into the receiver fabric I will need to flop it again using a BUFR clock. Now if there is skew between the BUFIO clock and BUFR clock then I will need some kind of FIFO to do a clock domain transfer of the bus before I put the data into the BRAM. Some how I was of the opinion that if I use a BUFR (or a derived clock by letting the BUFR drive an MMCM which drives a BUFG) to clock in the data then the tools will not pack in the registers into the ILOGIC cells. I was thinking that to allow the tools to do that the clock must be a clock from the BUFIO. To be honest I was thrown off by the figure in the clock resources user guide for V6 (Figure 1-22 page 28) which shows only the BUFIO clock going into the IOLOGIC cells. But from what I understand from you gentlemen, this is not a problem and I can use the BUFR clock to directly clock in the data. It also says this in the user guide that BUFR can drive  IOLOGIC as well as the fabric. Sorry for missing this detail. Bob I guess one of your first signature line applies to me :).  I had read the user guide but I guess the figure somehow got stuck in my head. 160 MHz is not a very fast clock so I could get away with just using a BUFR.

Please tell me if I am still confused or if you need further clarification.

Regards,

Sai

[sai.kilambi]

Hi Bob/Jim,

However I hope I am right about the fact that if I had indeed needed to use a BUFIO then I would have had to do a clock domain transfer right? Please confirm as I may need that detail in some future design.

Regards,

Sai.

[eteam00]

What you describe is a piece of cake for Virtex-6.  Yes, a single BUFR or BUFG should be entirely sufficient for the clock distribution purposes you describe.

Please look at the example design in this thread (post #3).  Although the description of this code uses Spartan-6 primitives and terms, the code (and timing contraints) are entirely non-specific -- usable as is for any Xilinx device family.  Note that the input register rank is forced to the IO logic region, to (essentially) eliminate most interconnect skews.

UPDATE:  The example code presumes SDR input data, not DDR input data.  You will need to explicitly instantiate IDDR blocks for input register ranks.

Update the timing contraints for the 160MHz operating frequency, install your BRAM, and you should be rolling in clover (so to speak).

If Jim Wu has a different recommendation, I would defer to his expertise without hesitation.

However I hope I am right about the fact that if I had indeed needed to use a BUFIO then I would have had to do a clock domain transfer right?

• If the BUFIO and BUFR are connected in series, YES you might need a (simple) clock domain transfer (e.g. posedge of clock BUFIO followed by negedge of clock BUFR).

• If the BUFIO and BUFR are connected in parallel (common input), per Jim Wu's description, NO you should not need a clock domain transfer circuit.

-- Bob Elkind