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Newbie
Posts: 1
Registered: ‎04-20-2008
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CRC (Cyclic REdundancy Check) for Verilog

i am brand new to Verilog, and have to make a serial and parallel CRC for my design class.

i am a little confused on how the CRC works though.   on wikipedia: http://en.wikipedia.org/wiki/Computation_of_CRC
the .gifs show the data being streamed in, then CRC'd with a full word of 0s.   Is this always the process? Are there always a full string of zeroes following the initial message, or was that an arbitrary case shown for demonstration purposes in that .gif?

thank you fellow engineersPreview Post
Expert Contributor
Posts: 360
Registered: ‎12-03-2007
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Re: CRC (Cyclic REdundancy Check) for Verilog

I've built a website - http://OutputLogic.com -  with online tool that generates a Verilog code for parallel CRC given data width and polynomial coefficients.

There is also a short post that describes a parallel CRC generation algorithm for Verilog.

 

Hope that helps

 

-evgeni

Newbie
Posts: 1
Registered: ‎02-17-2012
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Re: CRC (Cyclic REdundancy Check) for Verilog

nice one