Virtex® Family FPGAs

[yjgao]

Hi all,

    As far as I'm concerned, GCLK is used for clk input. Can I use it for clk output?

Thanks.

Best Regards.

[awillen]

The prefered way to output a clock signal is to use an ODDR primitive with the two data inputs set to constant 1 and 0.

Adrian

[bassman59]

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yjgao wrote:

Hi all,

    As far as I'm concerned, GCLK is used for clk input. Can I use it for clk output?

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The GCLK notion indicates that there is a dedicated path from the pin to a global clock buffer. If you don't use the pin as a clock input, then it's just another pin, and it can be used for outputs of any sort.

There is nothing special about clock outputs. You might want to enable the DCI series termination, though.

[mcgett]

>   As far as I'm concerned, GCLK is used for clk input. Can I use it for clk output?

Each FPGA family has a Pinout User Guide that describes the capabilities of each pin.  And pin name description that begins with the "IO" designation and be used as an Input or Ouput.

If the pin name includes the "GC" desigination this means that it can also connect to the dedicated clocking resources in the devices, but it does not limit the functionality to just a global clock input.

Adrian has also pointed out that you should use an ODDR or ODDR2 to drive the clock out of the device.  The simple topology would look like this.

  BUFG -> ODDR (clock input with D0=logic_1, D1=logic_0) -> OBUF

[kren]

Yes. There's no dedicated clock output on FPGA.