02-04-2012 05:11 PM - edited 02-04-2012 05:23 PM
I have problem like below picture.
I measured clock signal and data signal at FPGA Ball(Actually Via near Ball).
However, I found that clock and data signals are aligned at same edge.
thus, I want to add the delay time to the clock about 500ps in internal FPGA operation.
How can I solve this problem ? ( FPGA is Virtex6 )
Should i use IODELAYE1 ? or Are there the simple ways to modify timing ?
02-05-2012 11:28 PM
it depends on how you are capturing your data inside the FPGA.
One example, seen in a DDR-SDRAM interface:
The data is captured by by IOB-FFs. The clock for theseFFs is locally routed from the PAD via an IBUF to the FFs clock inputs. The delay between the clock pad and the FFs clock input is more than enough for this purpose, if not even too much. Of course this local clock routing need to be guarded by some constraints (maxskew etc.).
You camn use IODELAY blocks for finetuning, but before that you need some delay information from your actual data capture circuit.
If you have an other scheme, e.g. involving DCMs etc. things may be different.
How about using one of the high speed trtansceivers, if your device has one?
Have a nice synthesis
02-06-2012 04:49 AM - edited 02-06-2012 04:49 AM
There is no fixed 500pS +/- 0pS delay component. You can add a static delay, but the static delay varies considerably from device to device, and also varies considerably over the datasheet temperature and voltage range. In other words, every component inserted into the circuit path adds both delay and skew.
The datasheet of the device familyyou are using should include some of the delay figures which allow you to calculate this skew. Some of the path delay and skew is attributed to interconnect delay, which is primarily design dependent.
In order to complete your design analysis, you will also need (at least):
- worst-case source delays and skews between data and clock, from the source device, including both clock edges
- additional delays and skews from the circuit board layout
- clock period and serial data bit-rate
- target FPGA device family
If worst-case analysis suggests the original solution approach is not guaranteed to work, there are probably other design approaches and FPGA features -- depending on the FPGA device family -- which specifically address this type of design problem.
If you are interested in a precise and accurate fixed delay, the most reliable implementation is added circuit board trace length. The rule of thumb for circuit board trace delay is 150pS per inch, or 59pS per centimeter. You should consult your board fabrication for more accurate figures which depend somewhat on materials and tolerances in raw circuit board construction. A circuit board trace delay is likely to be much more consistent from board to board than circuit components on an FPGA or ASIC, and is essentially immune to variations in temperature and voltage.
-- Bob Elkind
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.