We're trying to use the DCI cascading feature on a Virtex-5 LX30T part.
From my understanding of the documentation (and I'll just go ahead and say the DCI cascading feature is underdocumented a bit), for my part, this is the minimum cascading configuration achievable (ie, least amount of VP/VN resistors, assuming all IO banks will use the same impedance):
CONFIG DCI_CASCADE = "15 11 13 17";
CONFIG DCI_CASCADE = "16 12 18";
CONFIG DCI_CASCADE = "3 1";
CONFIG DCI_CASCADE = "4 2";
Since you can't cascade through 0, and also since 1 and 2 don't have the required resistor pins, you MUST use 3 and 4 as masters. On the right and left side, you can make 15 and 16 masters and let all others be slaves.
Is my understanding correct?
